Searched refs:mmCP_MEC_CNTL (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 52 { 0x50000000, mmCP_MEC_CNTL },
1502 { 0x00000000, mmCP_MEC_CNTL },
1503 { 0x00000000, mmCP_MEC_CNTL },
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | smu8_smumgr.c | 192 mmCP_MEC_CNTL); in smu8_load_mec_firmware()
195 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); in smu8_load_mec_firmware()
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| H A D | fiji_smumgr.c | 213 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in fiji_start_avfs_btc()
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| H A D | polaris10_smumgr.c | 111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v9.c | 1211 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data); in kgd_gfx_v9_hqd_reset()
1212 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0); in kgd_gfx_v9_hqd_reset()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 319 #define mmCP_MEC_CNTL 0x208d macro
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| H A D | gfx_7_2_d.h | 322 #define mmCP_MEC_CNTL 0x208d macro
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| H A D | gfx_8_1_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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| H A D | gfx_8_0_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 135 #define mmCP_MEC_CNTL … macro
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| H A D | gc_9_1_offset.h | 135 #define mmCP_MEC_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 137 #define mmCP_MEC_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 2143 #define mmCP_MEC_CNTL … macro
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