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Searched refs:mmCP_MEC1_INSTR_PNTR (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h191 #define mmCP_MEC1_INSTR_PNTR … macro
H A Dgc_9_1_offset.h191 #define mmCP_MEC1_INSTR_PNTR … macro
H A Dgc_9_2_1_offset.h185 #define mmCP_MEC1_INSTR_PNTR … macro
H A Dgc_10_1_0_offset.h2193 #define mmCP_MEC1_INSTR_PNTR … macro
H A Dgc_10_3_0_offset.h2274 #define mmCP_MEC1_INSTR_PNTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c213 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
H A Dgfx_v10_0.c344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),