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Searched refs:mmCP_INT_CNTL_RING1 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c3287 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3289 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
3300 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3302 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h223 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_7_2_d.h223 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_8_1_d.h248 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_8_0_d.h247 #define mmCP_INT_CNTL_RING1 0x306b macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2470 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_9_1_offset.h2747 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_9_2_1_offset.h2685 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_10_1_0_offset.h4809 #define mmCP_INT_CNTL_RING1 … macro