Searched refs:mmCP_INT_CNTL_RING0 (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 222 #define mmCP_INT_CNTL_RING0 0x306a macro
|
| H A D | gfx_7_2_d.h | 222 #define mmCP_INT_CNTL_RING0 0x306a macro
|
| H A D | gfx_8_1_d.h | 247 #define mmCP_INT_CNTL_RING0 0x306a macro
|
| H A D | gfx_8_0_d.h | 246 #define mmCP_INT_CNTL_RING0 0x306a macro
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v8_0.c | 3859 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_enable_gui_idle_interrupt()
3866 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v8_0_enable_gui_idle_interrupt()
|
| H A D | gfx_v9_0.c | 2762 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v9_0_enable_gui_idle_interrupt()
2770 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v9_0_enable_gui_idle_interrupt()
|
| H A D | gfx_v10_0.c | 5396 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_get_cpg_int_cntl()
9066 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_set_gfx_eop_interrupt_state()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2468 #define mmCP_INT_CNTL_RING0 … macro
|
| H A D | gc_9_1_offset.h | 2745 #define mmCP_INT_CNTL_RING0 … macro
|
| H A D | gc_9_2_1_offset.h | 2683 #define mmCP_INT_CNTL_RING0 … macro
|
| H A D | gc_10_1_0_offset.h | 4807 #define mmCP_INT_CNTL_RING0 … macro
|