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Searched refs:mmCP_INT_CNTL_RING0 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2305 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_enable_gui_idle_interrupt()
2315 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v6_0_enable_gui_idle_interrupt()
3265 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3267 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3270 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3272 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3328 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_priv_reg_fault_state()
3330 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3333 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_priv_reg_fault_state()
3335 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
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/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_7_2_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_8_1_d.h247 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_8_0_d.h246 #define mmCP_INT_CNTL_RING0 0x306a macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2468 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_9_1_offset.h2745 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_9_2_1_offset.h2683 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_10_1_0_offset.h4807 #define mmCP_INT_CNTL_RING0 … macro