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Searched refs:mmCP_HQD_WG_STATE_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_d.h681 #define mmCP_HQD_WG_STATE_OFFSET 0x3275 macro
H A Dgfx_8_0_d.h681 #define mmCP_HQD_WG_STATE_OFFSET 0x3275 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2919 #define mmCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_9_1_offset.h3147 #define mmCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_9_2_1_offset.h3103 #define mmCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_10_1_0_offset.h5403 #define mmCP_HQD_WG_STATE_OFFSET … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4539 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
H A Dgfx_v10_0.c409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),