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Searched refs:mmCP_HQD_PQ_WPTR_HI (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v10_3.c213 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3()
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in hqd_load_v10_3()
348 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
362 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_dump()
H A Damdgpu_amdkfd_gfx_v9.c241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load()
373 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_dump()
H A Dgfx_v9_0.c278 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
3677 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3736 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3788 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_0_kiq_fini_register()
H A Dgfx_v10_0.c420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
6935 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
6998 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2933 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_9_1_offset.h3161 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_9_2_1_offset.h3117 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_10_1_0_offset.h5417 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_10_3_0_offset.h5050 #define mmCP_HQD_PQ_WPTR_HI … macro