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Searched refs:mmCP_HQD_PQ_RPTR (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h1546 { 0x00000000, mmCP_HQD_PQ_RPTR },
1551 { 0x00000000, mmCP_HQD_PQ_RPTR },
1556 { 0x00000000, mmCP_HQD_PQ_RPTR },
1561 { 0x00000000, mmCP_HQD_PQ_RPTR },
1566 { 0x00000000, mmCP_HQD_PQ_RPTR },
1571 { 0x00000000, mmCP_HQD_PQ_RPTR },
1576 { 0x00000000, mmCP_HQD_PQ_RPTR },
1581 { 0x00000000, mmCP_HQD_PQ_RPTR },
1586 { 0x00000000, mmCP_HQD_PQ_RPTR },
1591 { 0x00000000, mmCP_HQD_PQ_RPTR },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h577 #define mmCP_HQD_PQ_RPTR 0x324f macro
H A Dgfx_7_2_d.h590 #define mmCP_HQD_PQ_RPTR 0x324f macro
H A Dgfx_8_1_d.h640 #define mmCP_HQD_PQ_RPTR 0x324f macro
H A Dgfx_8_0_d.h640 #define mmCP_HQD_PQ_RPTR 0x324f macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2807 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v7_0_mqd_deactivate()
2907 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2924 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
H A Dgfx_v9_0.c251 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
3614 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v9_0_mqd_init()
3673 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, in gfx_v9_0_kiq_init_register()
3787 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); in gfx_v9_0_kiq_fini_register()
H A Dgfx_v8_0.c4388 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v8_0_deactivate_hqd()
4504 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v8_0_mqd_init()
H A Dgfx_v10_0.c393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
6885 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v10_0_compute_mqd_init()
6931 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, in gfx_v10_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2839 #define mmCP_HQD_PQ_RPTR … macro
H A Dgc_9_1_offset.h3067 #define mmCP_HQD_PQ_RPTR … macro
H A Dgc_9_2_1_offset.h3023 #define mmCP_HQD_PQ_RPTR … macro
H A Dgc_10_1_0_offset.h5323 #define mmCP_HQD_PQ_RPTR … macro
H A Dgc_10_3_0_offset.h4956 #define mmCP_HQD_PQ_RPTR … macro