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Searched refs:mmCP_HQD_PQ_DOORBELL_CONTROL (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c184 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
373 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v9.c248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load()
971 (RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) & in get_wave_count()
H A Damdgpu_amdkfd_gfx_v8.c208 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
H A Damdgpu_amdkfd_gfx_v10_3.c220 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in hqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c234 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
H A Dgfx_v9_0.c273 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
3588 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_0_mqd_init()
3705 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3775 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3830 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_0_kiq_fini_register()
3831 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
H A Dgfx_v10_0.c391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
6944 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v10_0_compute_mqd_init()
7070 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v10_0_kiq_init_register()
7122 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v10_0_kiq_init_register()
H A Dgfx_v8_0.c4442 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL), in gfx_v8_0_mqd_init()
4492 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v8_0_mqd_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h582 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
H A Dgfx_7_2_d.h595 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
H A Dgfx_8_1_d.h645 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
H A Dgfx_8_0_d.h645 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2849 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_9_1_offset.h3077 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_9_2_1_offset.h3033 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
H A Dgc_10_1_0_offset.h5333 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro