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Searched refs:mmCP_HQD_PQ_BASE_HI (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h1508 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1518 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1528 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1538 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c499 high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI)) in kgd_gfx_v9_hqd_is_occupied()
1147 high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI); in kgd_gfx_v9_hqd_get_pq_addr()
1195 high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI); in kgd_gfx_v9_hqd_reset()
H A Damdgpu_amdkfd_gfx_v7.c335 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
H A Damdgpu_amdkfd_gfx_v8.c367 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
H A Damdgpu_amdkfd_gfx_v10_3.c474 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) in hqd_is_occupied_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c488 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
H A Dgfx_v9_0.c250 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
3657 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, in gfx_v9_0_kiq_init_register()
H A Dgfx_v10_0.c392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
6942 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, in gfx_v10_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h576 #define mmCP_HQD_PQ_BASE_HI 0x324e macro
H A Dgfx_7_2_d.h589 #define mmCP_HQD_PQ_BASE_HI 0x324e macro
H A Dgfx_8_1_d.h639 #define mmCP_HQD_PQ_BASE_HI 0x324e macro
H A Dgfx_8_0_d.h639 #define mmCP_HQD_PQ_BASE_HI 0x324e macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2837 #define mmCP_HQD_PQ_BASE_HI macro
H A Dgc_9_1_offset.h3065 #define mmCP_HQD_PQ_BASE_HI macro
H A Dgc_9_2_1_offset.h3021 #define mmCP_HQD_PQ_BASE_HI macro
H A Dgc_10_1_0_offset.h5321 #define mmCP_HQD_PQ_BASE_HI macro
H A Dgc_10_3_0_offset.h4954 #define mmCP_HQD_PQ_BASE_HI macro