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Searched refs:mmCP_HQD_IQ_TIMER (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c397 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v8.c432 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10.c562 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
H A Dgfx_v8_0.c4519 tmp = RREG32(mmCP_HQD_IQ_TIMER); in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c3782 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); in gfx_v9_0_kiq_fini_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h589 #define mmCP_HQD_IQ_TIMER 0x325b macro
H A Dgfx_7_2_d.h602 #define mmCP_HQD_IQ_TIMER 0x325b macro
H A Dgfx_8_1_d.h652 #define mmCP_HQD_IQ_TIMER 0x325b macro
H A Dgfx_8_0_d.h652 #define mmCP_HQD_IQ_TIMER 0x325b macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2861 #define mmCP_HQD_IQ_TIMER … macro
H A Dgc_9_1_offset.h3089 #define mmCP_HQD_IQ_TIMER … macro
H A Dgc_9_2_1_offset.h3045 #define mmCP_HQD_IQ_TIMER … macro
H A Dgc_10_1_0_offset.h5345 #define mmCP_HQD_IQ_TIMER … macro
H A Dgc_10_3_0_offset.h4978 #define mmCP_HQD_IQ_TIMER … macro