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Searched refs:mmCP_HQD_IB_RPTR (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h587 #define mmCP_HQD_IB_RPTR 0x3259 macro
H A Dgfx_7_2_d.h600 #define mmCP_HQD_IB_RPTR 0x3259 macro
H A Dgfx_8_1_d.h650 #define mmCP_HQD_IB_RPTR 0x3259 macro
H A Dgfx_8_0_d.h650 #define mmCP_HQD_IB_RPTR 0x3259 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2857 #define mmCP_HQD_IB_RPTR … macro
H A Dgc_9_1_offset.h3085 #define mmCP_HQD_IB_RPTR … macro
H A Dgc_9_2_1_offset.h3041 #define mmCP_HQD_IB_RPTR … macro
H A Dgc_10_1_0_offset.h5341 #define mmCP_HQD_IB_RPTR … macro
H A Dgc_10_3_0_offset.h4974 #define mmCP_HQD_IB_RPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2916 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); in gfx_v7_0_mqd_init()
H A Dgfx_v9_0.c258 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
H A Dgfx_v10_0.c400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),