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Searched refs:mmCP_HQD_IB_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h588 #define mmCP_HQD_IB_CONTROL 0x325a macro
H A Dgfx_7_2_d.h601 #define mmCP_HQD_IB_CONTROL 0x325a macro
H A Dgfx_8_1_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
H A Dgfx_8_0_d.h651 #define mmCP_HQD_IB_CONTROL 0x325a macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c259 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
3624 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v9_0_mqd_init()
3783 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
H A Dgfx_v7_0.c2913 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
H A Dgfx_v10_0.c401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
6895 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v10_0_compute_mqd_init()
H A Dgfx_v8_0.c4514 tmp = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v8_0_mqd_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2859 #define mmCP_HQD_IB_CONTROL macro
H A Dgc_9_1_offset.h3087 #define mmCP_HQD_IB_CONTROL macro
H A Dgc_9_2_1_offset.h3043 #define mmCP_HQD_IB_CONTROL macro
H A Dgc_10_1_0_offset.h5343 #define mmCP_HQD_IB_CONTROL macro
H A Dgc_10_3_0_offset.h4976 #define mmCP_HQD_IB_CONTROL macro