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Searched refs:mmCPG_UTCL1_STATUS (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2665 #define mmCPG_UTCL1_STATUS … macro
H A Dgc_9_1_offset.h2917 #define mmCPG_UTCL1_STATUS … macro
H A Dgc_9_2_1_offset.h2851 #define mmCPG_UTCL1_STATUS … macro
H A Dgc_10_1_0_offset.h5157 #define mmCPG_UTCL1_STATUS … macro
H A Dgc_10_3_0_offset.h4822 #define mmCPG_UTCL1_STATUS … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c195 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
H A Dgfx_v10_0.c325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),