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Searched refs:mmCPC_INT_STATUS (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h273 #define mmCPC_INT_STATUS 0x30b5 macro
H A Dgfx_7_2_d.h275 #define mmCPC_INT_STATUS 0x30b5 macro
H A Dgfx_8_1_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
H A Dgfx_8_0_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2595 #define mmCPC_INT_STATUS … macro
H A Dgc_9_1_offset.h2865 #define mmCPC_INT_STATUS … macro
H A Dgc_9_2_1_offset.h2799 #define mmCPC_INT_STATUS … macro
H A Dgc_10_1_0_offset.h4937 #define mmCPC_INT_STATUS … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c5676 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v9_0_ring_emit_fence_kiq()