Searched refs:mmCPC_INT_CNTL (Results 1 – 15 of 15) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v7.c | 128 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 123 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 120 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in init_interrupts_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 151 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
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| H A D | gfx_v10_0.c | 9335 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
9338 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9345 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
9348 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 264 #define mmCPC_INT_CNTL 0x30b4 macro
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| H A D | gfx_7_2_d.h | 266 #define mmCPC_INT_CNTL 0x30b4 macro
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| H A D | gfx_8_1_d.h | 297 #define mmCPC_INT_CNTL 0x30b4 macro
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| H A D | gfx_8_0_d.h | 297 #define mmCPC_INT_CNTL 0x30b4 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2593 #define mmCPC_INT_CNTL … macro
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| H A D | gc_9_1_offset.h | 2863 #define mmCPC_INT_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 2797 #define mmCPC_INT_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 4935 #define mmCPC_INT_CNTL … macro
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| H A D | gc_10_3_0_offset.h | 4594 #define mmCPC_INT_CNTL … macro
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