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Searched refs:mmCGTT_WD_CLK_CTRL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c60 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
151 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
H A Dgfx_v10_0.c490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
7939 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); in gfx_v10_0_update_medium_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2403 #define mmCGTT_WD_CLK_CTRL 0xf086 macro
H A Dgfx_7_2_d.h2428 #define mmCGTT_WD_CLK_CTRL 0xf086 macro
H A Dgfx_8_1_d.h2646 #define mmCGTT_WD_CLK_CTRL 0xf086 macro
H A Dgfx_8_0_d.h2668 #define mmCGTT_WD_CLK_CTRL 0xf086 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6515 #define mmCGTT_WD_CLK_CTRL macro
H A Dgc_9_1_offset.h6737 #define mmCGTT_WD_CLK_CTRL macro
H A Dgc_9_2_1_offset.h6755 #define mmCGTT_WD_CLK_CTRL macro
H A Dgc_10_1_0_offset.h10141 #define mmCGTT_WD_CLK_CTRL macro
H A Dgc_10_3_0_offset.h9859 #define mmCGTT_WD_CLK_CTRL 0x5086
9843 #define mmCGTT_WD_CLK_CTRL global() macro
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