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Searched refs:mmCGTS_SM_CTRL_REG (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c81 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
212 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
H A Dsi.c535 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
634 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
732 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
812 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
892 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
H A Dgfx_v8_0.c302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
5456 data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_get_clockgating_state()
5656 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5667 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
5698 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5702 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v6_0.c2570 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2573 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
2605 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2608 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
H A Dgfx_v7_0.c3558 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3570 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
3590 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3593 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h298 #define mmCGTS_SM_CTRL_REG 0x2454 macro
H A Dgfx_7_0_d.h1480 #define mmCGTS_SM_CTRL_REG 0xf000 macro
H A Dgfx_7_2_d.h1501 #define mmCGTS_SM_CTRL_REG 0xf000 macro
H A Dgfx_8_1_d.h1662 #define mmCGTS_SM_CTRL_REG 0xf000 macro
H A Dgfx_8_0_d.h1694 #define mmCGTS_SM_CTRL_REG 0xf000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6303 #define mmCGTS_SM_CTRL_REG … macro
H A Dgc_9_1_offset.h6525 #define mmCGTS_SM_CTRL_REG … macro
H A Dgc_9_2_1_offset.h6537 #define mmCGTS_SM_CTRL_REG … macro