Home
last modified time | relevance | path

Searched refs:mmCGTS_CU0_TA_SQC_CTRL_REG (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c174 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
H A Dgfx_v8_0.c264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1487 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a macro
H A Dgfx_7_2_d.h1508 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a macro
H A Dgfx_8_1_d.h1669 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a macro
H A Dgfx_8_0_d.h1701 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6317 #define mmCGTS_CU0_TA_SQC_CTRL_REG macro
H A Dgc_9_1_offset.h6539 #define mmCGTS_CU0_TA_SQC_CTRL_REG macro
H A Dgc_9_2_1_offset.h6551 #define mmCGTS_CU0_TA_SQC_CTRL_REG macro