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Searched refs:mmATC_L2_CACHE_4K_DSM_CNTL (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h238 #define mmATC_L2_CACHE_4K_DSM_CNTL … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4.c797 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL); in gfx_v9_4_query_utc_edc_status()
963 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL); in gfx_v9_4_reset_ras_error_count()