Searched refs:mmATC_L2_CACHE_2M_DSM_CNTL (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_4.c | 703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
705 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
774 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL); in gfx_v9_4_query_utc_edc_status()
937 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
939 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
958 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL); in gfx_v9_4_reset_ras_error_count()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 240 #define mmATC_L2_CACHE_2M_DSM_CNTL … macro
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