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Searched refs:mipi_dsi_dcs_write_seq (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/panel/
H A Dpanel-himax-hx8394.c96 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
100 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
104 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
108 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
112 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
118 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
125 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
133 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
141 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, in hsd060bhw4_init_sequence()
151 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, in hsd060bhw4_init_sequence()
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H A Dpanel-visionox-r66451.c48 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); in visionox_r66451_on()
49 mipi_dsi_dcs_write_seq(dsi, 0xc2, in visionox_r66451_on()
52 mipi_dsi_dcs_write_seq(dsi, 0xd7, in visionox_r66451_on()
56 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80); in visionox_r66451_on()
57 mipi_dsi_dcs_write_seq(dsi, 0xde, in visionox_r66451_on()
60 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x04); in visionox_r66451_on()
61 mipi_dsi_dcs_write_seq(dsi, 0xe8, 0x00, 0x02); in visionox_r66451_on()
62 mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x00, 0x08); in visionox_r66451_on()
63 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); in visionox_r66451_on()
64 mipi_dsi_dcs_write_seq(dsi, 0xc4, in visionox_r66451_on()
[all …]
H A Dpanel-samsung-s6d7aa0.c70 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5); in s6d7aa0_lock()
71 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5); in s6d7aa0_lock()
73 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a); in s6d7aa0_lock()
75 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a); in s6d7aa0_lock()
76 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a); in s6d7aa0_lock()
78 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0xa5, 0xa5); in s6d7aa0_lock()
245 mipi_dsi_dcs_write_seq(dsi, MCS_OTP_RELOAD, 0x00, 0x10); in s6d7aa0_lsl080al02_init()
249 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x10); in s6d7aa0_lsl080al02_init()
252 mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x28); in s6d7aa0_lsl080al02_init()
256 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x04); in s6d7aa0_lsl080al02_init()
[all …]
H A Dpanel-xinpeng-xpp055c272.c71 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); in xpp055c272_init_sequence()
72 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
77 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25); in xpp055c272_init_sequence()
78 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00); in xpp055c272_init_sequence()
79 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
82 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
85 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
86 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
87 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
88 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30); in xpp055c272_init_sequence()
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H A Dpanel-samsung-s6e88a0-ams452ef01.c47 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
48 mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
58 mipi_dsi_dcs_write_seq(dsi, 0xca, in s6e88a0_ams452ef01_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
73 mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
74 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()
H A Dpanel-boe-bf060y8m-aj0.c61 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
62 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0x4c); in boe_bf060y8m_aj0_on()
63 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x10); in boe_bf060y8m_aj0_on()
64 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, DCS_ALLOW_HBM_RANGE); in boe_bf060y8m_aj0_on()
65 mipi_dsi_dcs_write_seq(dsi, 0xf8, in boe_bf060y8m_aj0_on()
75 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
76 mipi_dsi_dcs_write_seq(dsi, 0xc0, in boe_bf060y8m_aj0_on()
79 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x00, 0x00, 0x1f, 0x1f, in boe_bf060y8m_aj0_on()
82 mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x20, 0x04, 0x10, 0x12, 0x92, in boe_bf060y8m_aj0_on()
85 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x01, 0x2c, 0x00, 0x77, 0x3e); in boe_bf060y8m_aj0_on()
H A Dpanel-samsung-sofef00.c59 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
67 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
68 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
69 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
73 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
H A Dpanel-sony-td4353-jdi.c79 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in sony_td4353_jdi_on()
87 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, in sony_td4353_jdi_on()
97 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sony_td4353_jdi_on()
H A Dpanel-ebbg-ft8719.c71 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); in ebbg_ft8719_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in ebbg_ft8719_on()
H A Dpanel-sharp-ls060t1sx01.c52 mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13); in sharp_ls060_on()
53 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sharp_ls060_on()
/linux/include/drm/
H A Ddrm_mipi_dsi.h432 #define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) \ macro
/linux/Documentation/gpu/
H A Dtodo.rst502 The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are