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Searched refs:min_ttu_vblank (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c1025 double min_ttu_vblank; in dml1_rq_dlg_get_dlg_params() local
1164 min_ttu_vblank = dlg_sys_param->t_urg_wm_us; in dml1_rq_dlg_get_dlg_params()
1166 min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1168 min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1169 min_ttu_vblank = min_ttu_vblank + t_calc_us; in dml1_rq_dlg_get_dlg_params()
1171 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1179 DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1917 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml1_rq_dlg_get_dlg_params()
1918 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml1_rq_dlg_get_dlg_params()
H A Ddisplay_rq_dlg_helpers.c340 ttu_regs->min_ttu_vblank); in print__ttu_regs_st()
H A Ddisplay_mode_structs.h678 unsigned int min_ttu_vblank; member
H A Ddisplay_mode_vba.h80 dml_get_pipe_attr_decl(min_ttu_vblank);
H A Ddisplay_mode_vba.c141 dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c226 double min_ttu_vblank; in dml32_rq_dlg_get_dlg_reg() local
279 …min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From … in dml32_rq_dlg_get_dlg_reg()
282 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); in dml32_rq_dlg_get_dlg_reg()
552 ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml32_rq_dlg_get_dlg_reg()
609 ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml32_rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c266 dml_float_t min_ttu_vblank; in dml_rq_dlg_get_dlg_reg() local
322 min_ttu_vblank = dml_get_min_ttu_vblank_in_us(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
325 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); in dml_rq_dlg_get_dlg_reg()
501 disp_ttu_regs->min_ttu_vblank = (dml_uint_t)(min_ttu_vblank * refclk_freq_in_mhz); in dml_rq_dlg_get_dlg_reg()
557 ASSERT(disp_ttu_regs->min_ttu_vblank < (dml_uint_t) dml_pow(2, 24)); in dml_rq_dlg_get_dlg_reg()
H A Ddml2_translation_helper.c1525 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; in dml2_update_pipe_ctx_dchub_regs()
H A Ddisplay_mode_util.c306 dml_print("DML: min_ttu_vblank = 0x%x\n", ttu_regs->min_ttu_vblank); in dml_print_ttu_regs_st()
H A Ddisplay_mode_core_structs.h1981 dml_uint_t min_ttu_vblank; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c815 double min_ttu_vblank; in dml20_rq_dlg_get_dlg_params() local
931 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
933 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20_rq_dlg_get_dlg_params()
944 min_ttu_vblank); in dml20_rq_dlg_get_dlg_params()
1522 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml20_rq_dlg_get_dlg_params()
1523 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20_rq_dlg_get_dlg_params()
H A Ddisplay_rq_dlg_calc_20v2.c815 double min_ttu_vblank; in dml20v2_rq_dlg_get_dlg_params() local
931 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
933 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20v2_rq_dlg_get_dlg_params()
945 min_ttu_vblank); in dml20v2_rq_dlg_get_dlg_params()
1523 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml20v2_rq_dlg_get_dlg_params()
1524 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20v2_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c861 double min_ttu_vblank; in dml_rq_dlg_get_dlg_params() local
977 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
979 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml_rq_dlg_get_dlg_params()
992 min_ttu_vblank); in dml_rq_dlg_get_dlg_params()
1630 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params()
1631 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c927 double min_ttu_vblank = 0; in dml_rq_dlg_get_dlg_params() local
1045 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1047 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; in dml_rq_dlg_get_dlg_params()
1059 min_ttu_vblank); in dml_rq_dlg_get_dlg_params()
1719 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params()
1720 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_dchub_registers.h64 uint32_t min_ttu_vblank; member
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c367 MIN_TTU_VBLANK, pipe_regs->ttu_regs.min_ttu_vblank, in hubp401_setup_interdependent()
902 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, in hubp401_read_state()
959 MIN_TTU_VBLANK, &s->min_ttu_vblank); in hubp401_read_state()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c747 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, in hubp1_setup_interdependent()
1016 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, in hubp1_read_state_common()
1073 MIN_TTU_VBLANK, &s->min_ttu_vblank); in hubp1_read_state_common()
H A Ddcn10_hubp.h686 uint32_t min_ttu_vblank; member
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c293 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, in hubp2_setup_interdependent()
1247 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, in hubp2_read_state_common()
1304 MIN_TTU_VBLANK, &s->min_ttu_vblank); in hubp2_read_state_common()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c2623 || (old_ttu_regs.min_ttu_vblank != new_ttu_regs->min_ttu_vblank) in dcn401_detect_pipe_changes()
2640 old_ttu_regs.min_ttu_vblank = new_ttu_regs->min_ttu_vblank; in dcn401_detect_pipe_changes()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1620 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || in dcn20_detect_pipe_changes()
1638 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; in dcn20_detect_pipe_changes()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h1431 double min_ttu_vblank; member
H A Ddml2_core_shared.c11698 l->min_ttu_vblank = mode_lib->mp.MinTTUVBlank[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
11701 dml2_printf("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, l->min_ttu_vblank); in rq_dlg_get_dlg_reg()
11872 disp_ttu_regs->min_ttu_vblank = (unsigned int)(l->min_ttu_vblank * l->refclk_freq_in_mhz); in rq_dlg_get_dlg_reg()
11923 DML2_ASSERT(disp_ttu_regs->min_ttu_vblank < (unsigned int)math_pow(2, 24)); in rq_dlg_get_dlg_reg()
H A Ddml2_core_dcn4_calcs.c12459 l->min_ttu_vblank = mode_lib->mp.MinTTUVBlank[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
12462 dml2_printf("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, l->min_ttu_vblank); in rq_dlg_get_dlg_reg()
12622 disp_ttu_regs->min_ttu_vblank = (unsigned int)(l->min_ttu_vblank * l->refclk_freq_in_mhz); in rq_dlg_get_dlg_reg()
12673 DML2_ASSERT(disp_ttu_regs->min_ttu_vblank < (unsigned int)math_pow(2, 24)); in rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c3978 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; in commit_planes_for_stream()