Home
last modified time | relevance | path

Searched refs:meta_req_width (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c361 unsigned int meta_req_width; in get_meta_and_pte_attr() local
484 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
492 + meta_req_width; in get_meta_and_pte_attr()
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
545 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
490 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
497 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
498 + meta_req_width; in get_meta_and_pte_attr()
499 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
548 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
H A Ddisplay_rq_dlg_calc_20v2.c371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
490 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
497 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
498 + meta_req_width; in get_meta_and_pte_attr()
499 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
548 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c582 unsigned int meta_req_width; in get_surf_rq_param() local
725 meta_req_width = 1 << log2_meta_req_width; in get_surf_rq_param()
735 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_surf_rq_param()
736 + meta_req_width; in get_surf_rq_param()
737 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_surf_rq_param()
781 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_surf_rq_param()
H A Ddisplay_mode_vba.h832 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h397 unsigned int meta_req_width[],
912 unsigned int meta_req_width[],
H A Ddisplay_mode_vba_32.c493 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1309 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h629 unsigned int meta_req_width[DML2_MAX_PLANES]; member
1484 unsigned int *meta_req_width; member
H A Ddml2_core_shared.c9222 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k]; in CalculateMetaAndPTETimes()
10265 CalculateVMRowAndSwath_params->meta_req_width_luma = mode_lib->mp.meta_req_width; in dml2_core_shared_mode_programming()
11176 CalculateMetaAndPTETimes_params->meta_req_width = mode_lib->mp.meta_req_width; in dml2_core_shared_mode_programming()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_core_structs.h1007 dml_uint_t meta_req_width[__DML_NUM_PLANES__]; member
1363 dml_uint_t *meta_req_width; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c421 int meta_req_width[],
2395 &v->meta_req_width[k],
3028 v->meta_req_width,
6041 int meta_req_width[], argument
6111 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];