Home
last modified time | relevance | path

Searched refs:mem_parents (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c154 static const char * const mem_parents[] = { variable
454 TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
H A Dclk-mt8173-topckgen.c44 static const char * const mem_parents[] = { variable
532 MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,
H A Dclk-mt7622.c46 static const char * const mem_parents[] = { variable
387 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
H A Dclk-mt8135.c232 static const char * const mem_parents[] = { variable
377 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
H A Dclk-mt8365.c100 static const char * const mem_parents[] = { variable
412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
H A Dclk-mt2712.c137 static const char * const mem_parents[] = { variable
645 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
H A Dclk-mt2701.c153 static const char * const mem_parents[] = { variable
488 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
H A Dclk-mt6765.c170 static const char * const mem_parents[] = { variable
371 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,