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Searched refs:mec_int_cntl_reg (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3172 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state() local
3183 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3186 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3189 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3192 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3205 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3208 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3211 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3214 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3251 u32 mec_int_cntl_reg, mec_int_cntl; in gfx_v9_4_3_set_priv_reg_fault_state() local
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H A Dgfx_v12_1.c3888 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v12_1_xcc_set_compute_eop_interrupt_state() local
3899 mec_int_cntl_reg = SOC15_REG_OFFSET( in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3904 mec_int_cntl_reg = SOC15_REG_OFFSET( in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3909 mec_int_cntl_reg = SOC15_REG_OFFSET( in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3914 mec_int_cntl_reg = SOC15_REG_OFFSET( in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3929 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3934 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3937 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3942 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6304 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6315 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6318 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6321 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6324 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6337 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6339 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6342 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6344 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
H A Dgfx_v12_0.c4796 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v12_0_set_compute_eop_interrupt_state() local
4807 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4810 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4823 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4828 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4831 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4836 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c6023 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
6034 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6037 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6040 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6043 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6056 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6059 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6062 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6065 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c6453 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v11_0_set_compute_eop_interrupt_state() local
6464 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6467 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6470 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6473 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6486 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6491 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6494 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6499 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c9102 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
9113 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9116 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9119 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9122 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9135 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9138 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9141 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9144 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()