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Searched refs:mec_int_cntl (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3172 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state() local
3205 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3206 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3208 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3211 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3212 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3214 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3251 u32 mec_int_cntl_reg, mec_int_cntl; in gfx_v9_4_3_set_priv_reg_fault_state() local
3268 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); in gfx_v9_4_3_set_priv_reg_fault_state()
3269 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_set_priv_reg_fault_state()
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H A Dgfx_v12_1.c3888 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v12_1_xcc_set_compute_eop_interrupt_state() local
3929 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3930 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3932 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3934 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3937 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3938 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3940 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3942 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c6023 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
6056 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6057 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6059 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6062 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6063 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
6065 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c9102 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
9135 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9136 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9138 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9141 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9142 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9144 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()