Searched refs:mec_hdr (Results 1 – 7 of 7) sorted by relevance
2750 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v11_0_config_mec_cache_rs64() local2752 mec_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_mec_cache_rs64()2775 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v11_0_config_mec_cache_rs64()2776 mec_hdr->ucode_start_addr_hi << 30); in gfx_v11_0_config_mec_cache_rs64()2778 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v11_0_config_mec_cache_rs64()2832 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v11_0_config_gfx_rs64() local2835 mec_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_gfx_rs64()2890 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v11_0_config_gfx_rs64()2891 mec_hdr->ucode_start_addr_hi << 30); in gfx_v11_0_config_gfx_rs64()2893 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v11_0_config_gfx_rs64()[all …]
644 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_4_3_mec_init() local682 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_4_3_mec_init()686 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_4_3_mec_init()687 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v9_4_3_mec_init()689 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v9_4_3_mec_init()1744 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_4_3_xcc_cp_compute_load_microcode() local1756 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_4_3_xcc_cp_compute_load_microcode()1757 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1761 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1778 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); in gfx_v9_4_3_xcc_cp_compute_load_microcode()[all …]
2014 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v12_0_config_gfx_rs64() local2017 mec_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2072 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v12_0_config_gfx_rs64()2073 mec_hdr->ucode_start_addr_hi << 30); in gfx_v12_0_config_gfx_rs64()2075 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v12_0_config_gfx_rs64()2720 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v12_0_cp_compute_load_microcode_rs64() local2732 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; in gfx_v12_0_cp_compute_load_microcode_rs64()2733 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v12_0_cp_compute_load_microcode_rs64()2736 le32_to_cpu(mec_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_compute_load_microcode_rs64()2737 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); in gfx_v12_0_cp_compute_load_microcode_rs64()[all …]
1876 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_0_mec_init() local1902 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()1906 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_mec_init()1907 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v9_0_mec_init()1909 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v9_0_mec_init()3451 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_0_cp_compute_load_microcode() local3461 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()3462 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v9_0_cp_compute_load_microcode()3466 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_cp_compute_load_microcode()3479 mec_hdr->jt_offset); in gfx_v9_0_cp_compute_load_microcode()[all …]
2655 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v7_0_cp_compute_load_microcode() local2662 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()2663 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v7_0_cp_compute_load_microcode()2664 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()2666 mec_hdr->ucode_feature_version); in gfx_v7_0_cp_compute_load_microcode()2673 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_cp_compute_load_microcode()2674 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; in gfx_v7_0_cp_compute_load_microcode()
4370 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; in gfx_v10_0_mec_init() local4397 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()4400 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_mec_init()4401 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v10_0_mec_init()4403 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v10_0_mec_init()6539 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v10_0_cp_compute_load_microcode() local6550 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()6551 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v10_0_cp_compute_load_microcode()6555 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_compute_load_microcode()6593 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v10_0_cp_compute_load_microcode()[all …]
4256 const struct gfx_firmware_header_v1_0 *mec_hdr = in cik_cp_compute_load_microcode() local4261 radeon_ucode_print_gfx_hdr(&mec_hdr->header); in cik_cp_compute_load_microcode()4265 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in cik_cp_compute_load_microcode()4266 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; in cik_cp_compute_load_microcode()4270 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()