Searched refs:me_hdr (Results 1 – 4 of 4) sorted by relevance
2818 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_me_cache_rs64() local2820 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_me_cache_rs64()2875 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_me_cache_rs64()2876 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_me_cache_rs64()2878 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_me_cache_rs64()3022 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_gfx_rs64() local3028 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_gfx_rs64()3059 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_gfx_rs64()3060 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_gfx_rs64()3062 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_gfx_rs64()[all …]
2145 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_config_gfx_rs64() local2151 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2182 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v12_0_config_gfx_rs64()2183 (me_hdr->ucode_start_addr_lo >> 2)); in gfx_v12_0_config_gfx_rs64()2185 me_hdr->ucode_start_addr_hi>>2); in gfx_v12_0_config_gfx_rs64()2533 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_cp_gfx_load_me_microcode_rs64() local2539 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2542 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2546 le32_to_cpu(me_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2547 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()[all …]
6270 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v10_0_cp_gfx_load_me_microcode() local6276 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v10_0_cp_gfx_load_me_microcode()6279 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v10_0_cp_gfx_load_me_microcode()6282 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_gfx_load_me_microcode()6283 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); in gfx_v10_0_cp_gfx_load_me_microcode()6285 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, in gfx_v10_0_cp_gfx_load_me_microcode()6335 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v10_0_cp_gfx_load_me_microcode()6337 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_me_microcode()
3270 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v9_0_cp_gfx_load_microcode() local3281 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v9_0_cp_gfx_load_microcode()3286 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v9_0_cp_gfx_load_microcode()3313 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_cp_gfx_load_microcode()3314 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v9_0_cp_gfx_load_microcode()