| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_irq.c | 25 struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler); in mdp5_irq_error_handler() local
32 struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev); in mdp5_irq_error_handler()
33 drm_state_dump(mdp5_kms->dev, &p); in mdp5_irq_error_handler()
39 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_irq_preinstall() local
40 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_irq_preinstall()
43 mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); in mdp5_irq_preinstall()
44 mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); in mdp5_irq_preinstall()
51 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); in mdp5_irq_postinstall() local
52 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_irq_postinstall()
53 struct mdp_irq *error_handler = &mdp5_kms->error_handler; in mdp5_irq_postinstall()
[all …]
|
| H A D | mdp5_cmd_encoder.c | 13 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms()
23 struct mdp5_kms *mdp5_kms = get_kms(encoder); in pingpong_tearcheck_setup() local
30 if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) { in pingpong_tearcheck_setup()
42 vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE); in pingpong_tearcheck_setup()
61 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); in pingpong_tearcheck_setup()
62 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
65 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
67 mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); in pingpong_tearcheck_setup()
68 mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); in pingpong_tearcheck_setup()
69 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), in pingpong_tearcheck_setup()
[all …]
|
| H A D | mdp5_encoder.c | 13 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms()
24 struct mdp5_kms *mdp5_kms = get_kms(encoder); in mdp5_vid_encoder_mode_set() local
93 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), in mdp5_vid_encoder_mode_set()
96 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); in mdp5_vid_encoder_mode_set()
97 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); in mdp5_vid_encoder_mode_set()
98 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), in mdp5_vid_encoder_mode_set()
101 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_vid_encoder_mode_set()
102 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_vid_encoder_mode_set()
103 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); in mdp5_vid_encoder_mode_set()
104 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); in mdp5_vid_encoder_mode_set()
[all …]
|
| H A D | mdp5_smp.c | 32 struct mdp5_kms *get_kms(struct mdp5_smp *smp) in get_kms()
121 struct mdp5_kms *mdp5_kms = get_kms(smp); in mdp5_smp_calculate() local
122 int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg); in mdp5_smp_calculate()
167 struct mdp5_kms *mdp5_kms = get_kms(smp); in mdp5_smp_assign() local
168 struct drm_device *dev = mdp5_kms->dev; in mdp5_smp_assign()
257 struct mdp5_kms *mdp5_kms = get_kms(smp); in write_smp_alloc_regs() local
263 mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i), in write_smp_alloc_regs()
265 mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i), in write_smp_alloc_regs()
272 struct mdp5_kms *mdp5_kms = get_kms(smp); in write_smp_fifo_regs() local
275 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { in write_smp_fifo_regs()
[all …]
|
| H A D | mdp5_kms.h | 20 struct mdp5_kms { struct
71 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) argument
81 struct mdp5_kms *mdp5_kms; member
88 struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
171 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) in mdp5_write() argument
173 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_write()
174 writel(data, mdp5_kms->mmio + reg); in mdp5_write()
177 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) in mdp5_read() argument
179 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_read()
180 return readl(mdp5_kms->mmio + reg); in mdp5_read()
[all …]
|
| H A D | mdp5_pipe.c | 15 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_pipe_assign() local
25 old_global_state = mdp5_get_existing_global_state(mdp5_kms); in mdp5_pipe_assign()
30 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { in mdp5_pipe_assign()
31 struct mdp5_hw_pipe *cur = mdp5_kms->hwpipes[i]; in mdp5_pipe_assign()
64 for (j = i + 1; j < mdp5_kms->num_hwpipes; in mdp5_pipe_assign()
67 mdp5_kms->hwpipes[j]; in mdp5_pipe_assign()
94 if (mdp5_kms->smp) { in mdp5_pipe_assign()
101 ret = mdp5_smp_assign(mdp5_kms->smp, &new_global_state->smp, in mdp5_pipe_assign()
125 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_pipe_release() local
144 if (mdp5_kms->smp) { in mdp5_pipe_release()
[all …]
|
| H A D | mdp5_mixer.c | 19 static int get_right_pair_idx(struct mdp5_kms *mdp5_kms, int lm) in get_right_pair_idx() argument
28 for (i = 0; i < mdp5_kms->num_hwmixers; i++) { in get_right_pair_idx()
29 struct mdp5_hw_mixer *mixer = mdp5_kms->hwmixers[i]; in get_right_pair_idx()
43 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_mixer_assign() local
53 for (i = 0; i < mdp5_kms->num_hwmixers; i++) { in mdp5_mixer_assign()
54 struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i]; in mdp5_mixer_assign()
74 pair_idx = get_right_pair_idx(mdp5_kms, cur->lm); in mdp5_mixer_assign()
81 *r_mixer = mdp5_kms->hwmixers[pair_idx]; in mdp5_mixer_assign()
|
| H A D | mdp5_smp.h | 60 struct mdp5_kms;
69 struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,
|
| H A D | mdp5_cfg.h | 122 struct mdp5_kms;
133 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
|
| H A D | mdp5_cfg.c | 1440 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, in mdp5_cfg_init() argument
1443 struct drm_device *dev = mdp5_kms->dev; in mdp5_cfg_init()
|
| /linux/drivers/gpu/drm/msm/ |
| H A D | Makefile | 64 disp/mdp5/mdp5_kms.o \
|