Searched refs:mdp5_kms (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_irq.c | 25 struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler); in mdp5_irq_error_handler() local 32 struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev); in mdp5_irq_error_handler() 33 drm_state_dump(mdp5_kms->dev, &p); in mdp5_irq_error_handler() 39 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_irq_preinstall() local 40 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_irq_preinstall() 43 mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); in mdp5_irq_preinstall() 44 mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); in mdp5_irq_preinstall() 51 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); in mdp5_irq_postinstall() local 52 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_irq_postinstall() 53 struct mdp_irq *error_handler = &mdp5_kms->error_handler; in mdp5_irq_postinstall() [all …]
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| H A D | mdp5_cmd_encoder.c | 13 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms() 23 struct mdp5_kms *mdp5_kms = get_kms(encoder); in pingpong_tearcheck_setup() local 30 if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) { in pingpong_tearcheck_setup() 42 vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE); in pingpong_tearcheck_setup() 61 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); in pingpong_tearcheck_setup() 62 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup() 65 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup() 67 mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); in pingpong_tearcheck_setup() 68 mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); in pingpong_tearcheck_setup() 69 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), in pingpong_tearcheck_setup() [all …]
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| H A D | mdp5_encoder.c | 13 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms() 24 struct mdp5_kms *mdp5_kms = get_kms(encoder); in mdp5_vid_encoder_mode_set() local 93 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), in mdp5_vid_encoder_mode_set() 96 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); in mdp5_vid_encoder_mode_set() 97 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); in mdp5_vid_encoder_mode_set() 98 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), in mdp5_vid_encoder_mode_set() 101 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_vid_encoder_mode_set() 102 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_vid_encoder_mode_set() 103 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); in mdp5_vid_encoder_mode_set() 104 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); in mdp5_vid_encoder_mode_set() [all …]
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| H A D | mdp5_smp.h | 60 struct mdp5_kms; 69 struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,
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| H A D | mdp5_cfg.h | 122 struct mdp5_kms; 133 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
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