Home
last modified time | relevance | path

Searched refs:mc_readl (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/memory/tegra/
H A Dtegra20.c287 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
303 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
319 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra20_mc_block_dma()
330 return mc_readl(mc, rst->status) == 0; in tegra20_mc_dma_idling()
336 return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; in tegra20_mc_reset_status()
347 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra20_mc_unblock_dma()
470 count0 = mc_readl(mc, MC_STAT_EMC_COUNT_0); in tegra20_mc_stat_gather()
471 count1 = mc_readl(mc, MC_STAT_EMC_COUNT_1); in tegra20_mc_stat_gather()
472 clocks = mc_readl(mc, MC_STAT_EMC_CLOCKS); in tegra20_mc_stat_gather()
698 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_handle_irq()
[all …]
H A Dmc.c147 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
158 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
169 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
180 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
376 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); in tegra_mc_get_emem_device_count()
399 value = mc_readl(mc, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
409 value = mc_readl(mc, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
580 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra30_mc_handle_irq()
641 value = mc_readl(mc, status_reg); in tegra30_mc_handle_irq()
649 addr = mc_readl(mc, addr_hi_reg); in tegra30_mc_handle_irq()
[all …]
H A Dmc.h136 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) in mc_readl() function
H A Dtegra30-emc.c553 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
585 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
787 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
H A Dtegra210-emc-core.c844 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_do_clock_change()
1766 value = mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_detect()
H A Dtegra30.c1285 value = mc_readl(mc, client->regs.la.reg); in tegra30_mc_tune_client_latency()
H A Dtegra210-emc-cc-r21021.c976 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_r21021_set_clock()