Searched refs:mc_mask (Results 1 – 9 of 9) sorted by relevance
572 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { in radeon_vram_location()607 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; in radeon_gtt_location()1349 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in radeon_device_init()1351 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ in radeon_device_init()1353 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ in radeon_device_init()
1615 size_af = mc->mc_mask - mc->gtt_end; in r700_vram_gtt_location()
1401 size_af = mc->mc_mask - mc->gtt_end; in r600_vram_gtt_location()
278 u64 mc_mask; member
298 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); in amdgpu_gmc_gart_location()354 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); in amdgpu_gmc_agp_location()
1018 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v7_0_sw_init()
1133 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v8_0_sw_init()
1977 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v9_0_sw_init()
971 mac_cb->mc_mask, ETH_ALEN)) { in hns_mac_get_info()974 eth_broadcast_addr(mac_cb->mc_mask); in hns_mac_get_info()