Searched refs:max_sh_per_se (Results 1 – 14 of 14) sorted by relevance
128 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()131 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()150 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()196 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
1701 for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) { in fill_in_l2_l3_pcache()1758 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()1826 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()2091 gfx_info->max_sh_per_se; in kfd_topology_add_device()
2288 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
1339 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()1380 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()1473 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()1478 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()1482 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()1506 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()1554 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()1657 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()1674 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()1691 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()[all …]
1345 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_1_get_sa_active_bitmap()1391 adev->gfx.config.max_sh_per_se; in gfx_v12_1_setup_rb()1393 adev->gfx.config.max_sh_per_se; in gfx_v12_1_setup_rb()4018 adev->gfx.config.max_sh_per_se > 2) { in gfx_v12_1_get_cu_info()4022 adev->gfx.config.max_sh_per_se); in gfx_v12_1_get_cu_info()4028 adev->gfx.config.max_sh_per_se); in gfx_v12_1_get_cu_info()4033 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_1_get_cu_info()4034 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_1_get_cu_info()4042 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v12_1_get_cu_info()
1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()2536 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()2547 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()2551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()2554 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()2723 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()4635 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()7853 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()7858 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()7862 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()[all …]
1706 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()1748 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()1750 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()5751 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()5752 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
531 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in amdgpu_gfx_mqd_symmetrically_map_cu_mask()541 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
2017 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()2059 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()2061 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()7468 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()7552 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()7553 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
1747 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()1791 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
946 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
1849 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()4032 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
457 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()459 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
5655 UCHAR max_sh_per_se; member5668 UCHAR max_sh_per_se; member