Searched refs:max_sh_per_se (Results 1 – 13 of 13) sorted by relevance
128 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()131 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()150 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()196 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
66 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask_v12_1()91 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask_v12_1()
1701 for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) { in fill_in_l2_l3_pcache()1758 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()1826 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()2091 gfx_info->max_sh_per_se; in kfd_topology_add_device()
2288 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
457 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()459 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()254 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()887 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
747 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
1706 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()1748 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()1750 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()5726 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()5727 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
1665 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()1709 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
955 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
2547 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()4745 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
2235 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()2264 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
5655 UCHAR max_sh_per_se; member5668 UCHAR max_sh_per_se; member