| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager.c | 126 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()
129 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()
148 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()
194 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
|
| H A D | kfd_topology.c | 1744 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()
1812 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()
2072 gfx_info->max_sh_per_se; in kfd_topology_add_device()
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atomfirmware.c | 827 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
845 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
866 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
|
| H A D | gfx_v7_0.c | 1594 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1636 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1754 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1759 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1762 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1788 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3263 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4182 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4199 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4217 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
[all …]
|
| H A D | gfx_v8_0.c | 1662 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1679 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1726 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1759 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3433 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3484 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3595 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3600 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
[all …]
|
| H A D | amdgpu_debugfs.c | 130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
898 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
|
| H A D | amdgpu_gfx.h | 191 unsigned max_sh_per_se; member
|
| H A D | gfx_v9_0.c | 1671 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2500 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2511 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2515 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2518 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2681 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4628 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
7829 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7834 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7838 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
[all …]
|
| H A D | gfxhub_v2_1.c | 551 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
|
| H A D | gfx_v10_0.c | 4963 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4975 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
4979 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
4980 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
4991 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5018 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
5152 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
9965 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
10054 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
10055 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
[all …]
|
| H A D | amdgpu_atombios.c | 728 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
|
| H A D | gfx_v9_4_2.c | 1864 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1897 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
|
| H A D | gfx_v12_0.c | 1586 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()
1627 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
1629 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
5555 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()
5556 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
|
| H A D | gfx_v11_0.c | 1861 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1902 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1904 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
7061 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
7145 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7146 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
|
| H A D | amdgpu_discovery.c | 1532 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1576 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
|
| H A D | amdgpu_kms.c | 861 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
|
| H A D | amdgpu_device.c | 2514 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
4493 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
|
| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_kms.c | 459 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
461 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
|
| H A D | si.c | 3083 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3100 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3135 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3152 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3269 rdev->config.si.max_sh_per_se, in si_gpu_init()
3273 rdev->config.si.max_sh_per_se, in si_gpu_init()
3278 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
|
| H A D | cik.c | 3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
|
| H A D | radeon.h | 2125 unsigned max_sh_per_se; member
2156 unsigned max_sh_per_se; member
|
| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atomfirmware.h | 1791 uint8_t max_sh_per_se; member
1811 uint8_t max_sh_per_se; member
1836 uint8_t max_sh_per_se; member
1871 uint8_t max_sh_per_se; member
1912 uint8_t max_sh_per_se; member
|
| H A D | atombios.h | 5655 UCHAR max_sh_per_se; member
5668 UCHAR max_sh_per_se; member
|