Home
last modified time | relevance | path

Searched refs:max_pstate (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/acpi/
H A Dprocessor_thermal.c279 int max_pstate; in processor_set_cur_state() local
288 max_pstate = cpufreq_get_max_state(pr->id); in processor_set_cur_state()
293 if (state <= max_pstate) { in processor_set_cur_state()
298 cpufreq_set_cur_state(pr->id, max_pstate); in processor_set_cur_state()
300 state - max_pstate, false); in processor_set_cur_state()
/linux/drivers/cpufreq/
H A Dintel_pstate.c141 int max_pstate; member
542 return cpu->pstate.max_pstate; in intel_pstate_freq_to_hwp_rel()
1142 unsigned int max_freq = cpu->pstate.max_pstate * scaling; in intel_pstate_update_freq_limits()
1160 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); in __intel_pstate_get_hwp_cap()
1519 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; in show_turbo_pct()
1588 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; in store_no_turbo()
2058 if (pstate > cpudata->pstate.max_pstate) in atom_get_val()
2104 int_tofp(cpudata->pstate.max_pstate - in atom_get_vid()
2164 int max_pstate; in core_get_max_pstate() local
2169 max_pstate = (plat_info >> 8) & 0xFF; in core_get_max_pstate()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c636 uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0; in dcn314_clk_mgr_helper_populate_bw_params() local
645 max_pstate = i; in dcn314_clk_mgr_helper_populate_bw_params()
698 if (max_pstate != min_pstate || i == 0) { in dcn314_clk_mgr_helper_populate_bw_params()
703 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
704 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage; in dcn314_clk_mgr_helper_populate_bw_params()
710 clock_table->DfPstateTable[max_pstate].WckRatio); in dcn314_clk_mgr_helper_populate_bw_params()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c1046 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0; in dcn35_clk_mgr_helper_populate_bw_params() local
1059 max_pstate = entry_idx; in dcn35_clk_mgr_helper_populate_bw_params()
1064 min_pstate = max_pstate; in dcn35_clk_mgr_helper_populate_bw_params()
1129 if (max_pstate != min_pstate || i == 0) { in dcn35_clk_mgr_helper_populate_bw_params()
1134 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk; in dcn35_clk_mgr_helper_populate_bw_params()
1135 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage; in dcn35_clk_mgr_helper_populate_bw_params()
1143 clock_table->MemPstateTable[max_pstate].WckRatio); in dcn35_clk_mgr_helper_populate_bw_params()