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Searched refs:max_banks (Results 1 – 2 of 2) sorted by relevance

/linux/arch/x86/events/amd/
H A Diommu.c42 u8 max_banks; member
159 int max_banks = piommu->max_banks; in get_next_avail_iommu_bnk_cntr() local
166 for (bank = 0; bank < max_banks; bank++) { in get_next_avail_iommu_bnk_cntr()
190 int max_banks, max_cntrs; in clear_avail_iommu_bnk_cntr() local
193 max_banks = perf_iommu->max_banks; in clear_avail_iommu_bnk_cntr()
196 if ((bank > max_banks) || (cntr > max_cntrs)) in clear_avail_iommu_bnk_cntr()
433 perf_iommu->max_banks = amd_iommu_pc_get_max_banks(idx); in init_one_iommu()
437 !perf_iommu->max_banks || in init_one_iommu()
448 idx, perf_iommu->max_banks, perf_iommu->max_counters); in init_one_iommu()
/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c497 u8 max_banks; member
951 cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); in cadence_nand_get_caps()
3030 if (cs >= cdns_ctrl->caps2.max_banks) { in cadence_nand_chip_init()
3033 cs, cdns_ctrl->caps2.max_banks); in cadence_nand_chip_init()
3096 int max_cs = cdns_ctrl->caps2.max_banks; in cadence_nand_chips_init()