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Searched refs:max_allow_delay_us (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn6_stage_optimizers.c132 *allow_delay_us = (double)pmo->ip_caps->fams2.max_allow_delay_us; in dcn6_get_params_for_pstate_type()
137 *allow_delay_us = (double)pmo->ip_caps->fams2.max_allow_delay_us; /* TODO placeholder */ in dcn6_get_params_for_pstate_type()
170 const double max_allow_delay_us, in dcn6_is_timing_group_schedulable() argument
222 group_pstate_meta->disallow_time_us <= max_allow_delay_us; in dcn6_is_timing_group_schedulable()
229 const double max_allow_delay_us, in dcn6_is_pstate_schedulable() argument
256 max_allow_delay_us, in dcn6_is_pstate_schedulable()
329 if (schedulable && max_disallow_time_us < max_allow_delay_us) { in dcn6_is_pstate_schedulable()
368 if (schedulable && max_disallow_time_us < max_allow_delay_us) { in dcn6_is_pstate_schedulable()
397 max_disallow_time_us < max_allow_delay_us) { in dcn6_is_pstate_schedulable()
683 double max_allow_delay_us, in dcn6_build_pstate_meta_per_stream() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn6_calcs_dchub.c1766 double max_allow_delay_us, in dcn6_calculate_pstate_schedule_admissibility()
1850 if (disallow_window_us[cur_id] > max_allow_delay_us) in dcn6_calculate_pstate_schedule_admissibility()
1868 if (sum_of_disallow_windows_us < max_allow_delay_us) { in dcn6_calculate_pstate_schedule_admissibility()
1912 if (sum_of_disallow_windows_us < max_allow_delay_us) { in dcn6_calculate_pstate_schedule_admissibility()
1982 if (max_disallow_window_us >= max_allow_delay_us)
1714 dcn6_calculate_pstate_schedule_admissibility(uint32_t num_active_planes,double max_allow_delay_us,double min_allow_width_us,const uint32_t timing_group_id[DML2_MAX_PLANES],uint32_t timing_group_count,const double frame_time_us[DML2_MAX_PLANES],const double allow_start_us[DML2_MAX_PLANES],const double allow_end_us[DML2_MAX_PLANES],const enum dml2_pstate_method pstate_method[DML2_MAX_PLANES],const bool is_drr[DML2_MAX_DCN_PIPES],double allow_window_us[DML2_MAX_DCN_PIPES],double disallow_window_us[DML2_MAX_DCN_PIPES],bool * pstate_admissible) dcn6_calculate_pstate_schedule_admissibility() argument
H A Ddml2_core_dcn5_funcs_mode_programming.c1580 fams2_global_config->max_allow_delay_us = mode_lib->ip_caps.fams2.max_allow_delay_us; in dcn5_populate_global_fams2_programming()
H A Ddml2_core_dcn5_calcs_dchub.c5848 arb_param->pstate_stall_threshold = (unsigned int)(mode_lib->ip_caps.fams2.max_allow_delay_us * refclk_freq_in_mhz); in dcn5_rq_dlg_get_arb_params()