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Searched refs:mask1 (Results 1 – 25 of 60) sorted by relevance

123

/linux/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c100 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
102 mask1 = create_cpumask(); in create_cpumask_set()
103 if (!mask1) in create_cpumask_set()
108 bpf_cpumask_release(mask1); in create_cpumask_set()
115 bpf_cpumask_release(mask1); in create_cpumask_set()
123 bpf_cpumask_release(mask1); in create_cpumask_set()
130 *out1 = mask1; in create_cpumask_set()
254 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
260 mask1 = create_cpumask(); in BPF_PROG()
261 if (!mask1) in BPF_PROG()
318 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
365 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
407 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
573 _global_mask_array_rcu(struct bpf_cpumask ** mask0,struct bpf_cpumask ** mask1) _global_mask_array_rcu() argument
755 struct bpf_cpumask *mask1, *mask2; BPF_PROG() local
[all...]
/linux/sound/pci/ice1712/
H A Dwm8776.c135 .mask1 = WM8776_DACVOL_MASK,
145 .mask1 = WM8776_DAC_PL_LL,
153 .mask1 = WM8776_DAC_DZCEN,
161 .mask1 = WM8776_HPVOL_MASK,
171 .mask1 = WM8776_PWR_HPPD,
179 .mask1 = WM8776_VOL_HPZCEN,
187 .mask1 = WM8776_OUTMUX_AUX,
193 .mask1 = WM8776_OUTMUX_BYPASS,
199 .mask1 = WM8776_DAC_IZD,
206 .mask1 = WM8776_PHASE_INVERTL,
[all …]
H A Dwm8766.c36 .mask1 = WM8766_VOL_MASK,
47 .mask1 = WM8766_VOL_MASK,
58 .mask1 = WM8766_VOL_MASK,
67 .mask1 = WM8766_DAC2_MUTE1,
74 .mask1 = WM8766_DAC2_MUTE2,
81 .mask1 = WM8766_DAC2_MUTE3,
88 .mask1 = WM8766_PHASE_INVERT1,
94 .mask1 = WM8766_PHASE_INVERT2,
100 .mask1 = WM8766_PHASE_INVERT3,
106 .mask1 = WM8766_DAC2_DEEMP1,
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument
52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update() argument
80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set() argument
96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_set()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
180 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
199 reg1 ## __ ## mask1 ## _MASK,\
201 reg1 ## __ ## mask1 ## _MASK,\
202 ~reg1 ## __ ## mask1 ## _MASK \
/linux/fs/orangefs/
H A Dorangefs-debugfs.c106 __u64 mask1; member
499 c_mask.mask1, in orangefs_debug_write()
586 (unsigned long long *)&(cdm_array[i].mask1), in orangefs_prepare_cdm_array()
797 if ((mask->mask1 & cdm_array[index].mask1) || in do_c_string()
841 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && in check_amalgam_keyword()
848 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && in check_amalgam_keyword()
917 (**sane_mask).mask1 = (**sane_mask).mask1 | cdm_array[i].mask1; in do_c_mask()
942 client_debug_mask.mask1 = mask2_info.mask1_value; in orangefs_debugfs_new_client_mask()
948 (unsigned long long)client_debug_mask.mask1, in orangefs_debugfs_new_client_mask()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
203 reg1 ## __ ## mask1 ## _MASK,\
205 reg1 ## __ ## mask1 ## _MASK,\
206 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
210 reg1 ## __ ## mask1 ## _MASK,\
212 reg1 ## __ ## mask1 ## _MASK,\
213 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
205 reg1 ## __ ## mask1 ## _MASK,\
207 reg1 ## __ ## mask1 ## _MASK,\
208 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
184 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
198 reg1 ## __ ## mask1 ## _MASK,\
200 reg1 ## __ ## mask1 ## _MASK,\
201 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
188 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
200 reg1 ## __ ## mask1 ## _MASK,\
202 reg1 ## __ ## mask1 ## _MASK,\
203 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
195 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
209 reg1 ## __ ## mask1 ## _MASK,\
211 reg1 ## __ ## mask1 ## _MASK,\
212 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/
H A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
161 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
163 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
165 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
175 reg1 ## __ ## mask1 ## _MASK,\
177 reg1 ## __ ## mask1 ## _MASK,\
179 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
183 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
185 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
197 reg1 ## __ ## mask1 ## _MASK,\
199 reg1 ## __ ## mask1 ## _MASK,\
201 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
162 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
164 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
166 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
176 reg1 ## __ ## mask1 ## _MASK,\
178 reg1 ## __ ## mask1 ## _MASK,\
180 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
H A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
175 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
189 reg1 ## __ ## mask1 ## _MASK,\
191 reg1 ## __ ## mask1 ## _MASK,\
192 ~reg1 ## __ ## mask1 ## _MASK \
/linux/include/linux/
H A Dcpumask.h409 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
410 for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
427 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
428 for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
444 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
445 for_each_or_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
491 unsigned int cpumask_any_and_but(const struct cpumask *mask1, in cpumask_any_and_but() argument
501 i = cpumask_first_and(mask1, mask2); in cpumask_any_and_but()
505 return cpumask_next_and(cpu, mask1, mask2); in cpumask_any_and_but()
518 unsigned int cpumask_any_andnot_but(const struct cpumask *mask1, in cpumask_any_andnot_but() argument
[all …]
/linux/drivers/soc/fsl/qe/
H A Dgpio.c240 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
259 if (sregs->cpdata & mask1) in qe_pin_set_dedicated()
260 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated()
262 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated()
265 qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
/linux/arch/alpha/kernel/
H A Dsys_rawhide.c102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
111 mask1 = 1 << irq; in rawhide_mask_and_ack_irq()
112 mask = ~mask1 | hose_irq_masks[hose]; in rawhide_mask_and_ack_irq()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
H A Dsys_titan.c69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
74 mask1 = mask & titan_cpu_irq_affinity[1]; in titan_update_irq_hw()
79 else if (bcpu == 1) mask1 |= isa_enable; in titan_update_irq_hw()
93 *dim1 = mask1; in titan_update_irq_hw()
/linux/arch/mips/sgi-ip27/
H A Dip27-nmi.c127 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
131 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); in nmi_dump_hub_irq()
134 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); in nmi_dump_hub_irq()
140 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); in nmi_dump_hub_irq()
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
79 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
81 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
82 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
123 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
125 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
126 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/pcmcia/
H A Dtcic.c241 u_int mask1; in irq_scan() local
252 mask1 = 0; in irq_scan()
256 mask1 |= (1 << i); in irq_scan()
258 if ((mask1 & (1 << i)) && (try_irq(i) != 0)) { in irq_scan()
259 mask1 ^= (1 << i); in irq_scan()
263 if (mask1) { in irq_scan()
270 mask1 |= (1 << i); in irq_scan()
278 if (mask1 & (1<<i)) in irq_scan()
279 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); in irq_scan()
282 return mask1; in irq_scan()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
128 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
130 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
131 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

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