xref: /freebsd/sys/dev/mlx5/mlx5_ifc.h (revision 07f780cb7f8eab1aa6e84d3ed6785144d0d3cc47) 
1 /*-
2  * Copyright (c) 2013-2020, Mellanox Technologies.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #ifndef MLX5_IFC_H
27 #define MLX5_IFC_H
28 
29 /*
30  * Special UID that marks a resource (e.g. an EQ) as shared, so that
31  * objects owned by a user context (DEVX uid) may reference it.
32  */
33 #define	MLX5_SHARED_RESOURCE_UID	0xffff
34 
35 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
36 
37 enum {
38 	MLX5_EVENT_TYPE_NOTIFY_ANY				   = 0x0,
39 	MLX5_EVENT_TYPE_COMP                                       = 0x0,
40 	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
41 	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
42 	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
43 	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
44 	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
45 	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
46 	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
47 	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
48 	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
49 	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
50 	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
51 	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
52 	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
53 	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
54 	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
55 	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
56 	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
57 	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
58 	MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
59 	MLX5_EVENT_TYPE_XRQ_ERROR				   = 0x18,
60 	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
61 	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
62 	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
63 	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
64 	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
65 	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
66 	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
67 	MLX5_EVENT_TYPE_CMD                                        = 0xa,
68 	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
69 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
70 	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
71 	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
72 	MLX5_EVENT_TYPE_OBJECT_CHANGE                              = 0x27,
73 };
74 
75 enum {
76 	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
77 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
78 	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
79 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
80 	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
81 };
82 
83 enum {
84 	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
85 };
86 
87 enum {
88 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
89 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
90 };
91 
92 enum {
93 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 	MLX5_OBJ_TYPE_MKEY = 0xff01,
95 	MLX5_OBJ_TYPE_QP = 0xff02,
96 	MLX5_OBJ_TYPE_PSV = 0xff03,
97 	MLX5_OBJ_TYPE_RMP = 0xff04,
98 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 	MLX5_OBJ_TYPE_RQ = 0xff06,
100 	MLX5_OBJ_TYPE_SQ = 0xff07,
101 	MLX5_OBJ_TYPE_TIR = 0xff08,
102 	MLX5_OBJ_TYPE_TIS = 0xff09,
103 	MLX5_OBJ_TYPE_DCT = 0xff0a,
104 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 	MLX5_OBJ_TYPE_RQT = 0xff0e,
106 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 	MLX5_OBJ_TYPE_CQ = 0xff10,
108 };
109 
110 enum {
111 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
112 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
113 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
114 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
115 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
116 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
117 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
118 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
119 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
120 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
121 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
122 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
123 	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
124 	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
125 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
126 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
127 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
128 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
129 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
130 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
131 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
132 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
133 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
134 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
135 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
136 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
137 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
138 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
139 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
140 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
141 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
142 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
143 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
144 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
145 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
146 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
147 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
148 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
149 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
150 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
151 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
152 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
153 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
154 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
155 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
156 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
157 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
158 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
159 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
160 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
161 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
162 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
163 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
164 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
165 	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
166 	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
167 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
168 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
169 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
170 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
171 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
172 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
173 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
174 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
175 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
176 
177 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
178 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
179 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
180 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
181 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
182 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
183 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
184 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
185 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
186 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
187 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
188 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
189 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
190 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
191 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
192 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
193 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
194 	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
195 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
196 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
197 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
198 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
199 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
200 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
201 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
202 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
203 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
204 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
205 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
206 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
207 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
208 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
209 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
210 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
211 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
212 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
213 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
214 	MLX5_CMD_OP_NOP                           = 0x80d,
215 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
216 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
217 	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
218 	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
219 	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
220 	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
221 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
222 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
223 	MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS       = 0x819,
224 	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
225 	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
226 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
227 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
228 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
229 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
230 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
231 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
232 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
233 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
234 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
235 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
236 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
237 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
238 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
239 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
240 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
241 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
242 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
243 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
244 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
245 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
246 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
247 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
248 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
249 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
250 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
251 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
252 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
253 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
254 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
255 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
256 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
257 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
258 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
259 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
260 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
261 	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
262 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
263 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
264 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
265 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
266 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
267 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
268 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
269 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
270 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
271 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
272 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
273 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
274 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
275 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
276 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
277 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
278 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
279 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
280 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
281 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
282 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
283 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
284 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
285 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
286 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
287 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
288 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
289 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
290 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
291 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
292 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
293 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
294 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
295 	MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
296 	MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
297 	MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
298 	MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
299 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
300 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
301 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
302 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
303 };
304 
305 /* Valid range for general commands that don't work over an object */
306 enum {
307 	MLX5_CMD_OP_GENERAL_START = 0xb00,
308 	MLX5_CMD_OP_GENERAL_END = 0xd00,
309 };
310 
311 enum {
312 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
313 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
314 };
315 
316 enum {
317 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
318 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
319 	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
320 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
321 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
322 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
323 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
324 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
325 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
326 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
327 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
328 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
329 };
330 
331 enum {
332 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 1ULL << 0x13,
333 };
334 
335 enum {
336 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
337 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
338 };
339 
340 enum {
341 	MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
342 };
343 
344 enum {
345 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
346 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
347 };
348 
349 enum {
350 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
351 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
352 };
353 
354 struct mlx5_ifc_flow_table_fields_supported_bits {
355 	u8         outer_dmac[0x1];
356 	u8         outer_smac[0x1];
357 	u8         outer_ether_type[0x1];
358 	u8         outer_ip_version[0x1];
359 	u8         outer_first_prio[0x1];
360 	u8         outer_first_cfi[0x1];
361 	u8         outer_first_vid[0x1];
362 	u8         reserved_1[0x1];
363 	u8         outer_second_prio[0x1];
364 	u8         outer_second_cfi[0x1];
365 	u8         outer_second_vid[0x1];
366 	u8         outer_ipv6_flow_label[0x1];
367 	u8         outer_sip[0x1];
368 	u8         outer_dip[0x1];
369 	u8         outer_frag[0x1];
370 	u8         outer_ip_protocol[0x1];
371 	u8         outer_ip_ecn[0x1];
372 	u8         outer_ip_dscp[0x1];
373 	u8         outer_udp_sport[0x1];
374 	u8         outer_udp_dport[0x1];
375 	u8         outer_tcp_sport[0x1];
376 	u8         outer_tcp_dport[0x1];
377 	u8         outer_tcp_flags[0x1];
378 	u8         outer_gre_protocol[0x1];
379 	u8         outer_gre_key[0x1];
380 	u8         outer_vxlan_vni[0x1];
381 	u8         outer_geneve_vni[0x1];
382 	u8         outer_geneve_oam[0x1];
383 	u8         outer_geneve_protocol_type[0x1];
384 	u8         outer_geneve_opt_len[0x1];
385 	u8         reserved_2[0x1];
386 	u8         source_eswitch_port[0x1];
387 
388 	u8         inner_dmac[0x1];
389 	u8         inner_smac[0x1];
390 	u8         inner_ether_type[0x1];
391 	u8         inner_ip_version[0x1];
392 	u8         inner_first_prio[0x1];
393 	u8         inner_first_cfi[0x1];
394 	u8         inner_first_vid[0x1];
395 	u8         reserved_4[0x1];
396 	u8         inner_second_prio[0x1];
397 	u8         inner_second_cfi[0x1];
398 	u8         inner_second_vid[0x1];
399 	u8         inner_ipv6_flow_label[0x1];
400 	u8         inner_sip[0x1];
401 	u8         inner_dip[0x1];
402 	u8         inner_frag[0x1];
403 	u8         inner_ip_protocol[0x1];
404 	u8         inner_ip_ecn[0x1];
405 	u8         inner_ip_dscp[0x1];
406 	u8         inner_udp_sport[0x1];
407 	u8         inner_udp_dport[0x1];
408 	u8         inner_tcp_sport[0x1];
409 	u8         inner_tcp_dport[0x1];
410 	u8         inner_tcp_flags[0x1];
411 	u8         reserved_5[0x9];
412 
413 	u8         reserved_6[0x1a];
414 	u8         bth_dst_qp[0x1];
415 	u8         reserved_7[0x4];
416 	u8         source_sqn[0x1];
417 
418 	u8         reserved_8[0x20];
419 };
420 
421 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
422 	u8         ingress_general_high[0x20];
423 
424 	u8         ingress_general_low[0x20];
425 
426 	u8         ingress_policy_engine_high[0x20];
427 
428 	u8         ingress_policy_engine_low[0x20];
429 
430 	u8         ingress_vlan_membership_high[0x20];
431 
432 	u8         ingress_vlan_membership_low[0x20];
433 
434 	u8         ingress_tag_frame_type_high[0x20];
435 
436 	u8         ingress_tag_frame_type_low[0x20];
437 
438 	u8         egress_vlan_membership_high[0x20];
439 
440 	u8         egress_vlan_membership_low[0x20];
441 
442 	u8         loopback_filter_high[0x20];
443 
444 	u8         loopback_filter_low[0x20];
445 
446 	u8         egress_general_high[0x20];
447 
448 	u8         egress_general_low[0x20];
449 
450 	u8         reserved_at_1c0[0x40];
451 
452 	u8         egress_hoq_high[0x20];
453 
454 	u8         egress_hoq_low[0x20];
455 
456 	u8         port_isolation_high[0x20];
457 
458 	u8         port_isolation_low[0x20];
459 
460 	u8         egress_policy_engine_high[0x20];
461 
462 	u8         egress_policy_engine_low[0x20];
463 
464 	u8         ingress_tx_link_down_high[0x20];
465 
466 	u8         ingress_tx_link_down_low[0x20];
467 
468 	u8         egress_stp_filter_high[0x20];
469 
470 	u8         egress_stp_filter_low[0x20];
471 
472 	u8         egress_hoq_stall_high[0x20];
473 
474 	u8         egress_hoq_stall_low[0x20];
475 
476 	u8         reserved_at_340[0x440];
477 };
478 
479 struct mlx5_ifc_flow_table_prop_layout_bits {
480 	u8         ft_support[0x1];
481 	u8         reserved_at_1[0x1];
482 	u8         flow_counter[0x1];
483 	u8         flow_modify_en[0x1];
484 	u8         modify_root[0x1];
485 	u8         identified_miss_table_mode[0x1];
486 	u8         flow_table_modify[0x1];
487 	u8         reformat[0x1];
488 	u8         decap[0x1];
489 	u8         reserved_at_9[0x1];
490 	u8         pop_vlan[0x1];
491 	u8         push_vlan[0x1];
492 	u8         reserved_at_c[0x1];
493 	u8         pop_vlan_2[0x1];
494 	u8         push_vlan_2[0x1];
495 	u8         reformat_and_vlan_action[0x1];
496 	u8         reserved_at_10[0x1];
497 	u8         sw_owner[0x1];
498 	u8         reformat_l3_tunnel_to_l2[0x1];
499 	u8         reformat_l2_to_l3_tunnel[0x1];
500 	u8         reformat_and_modify_action[0x1];
501 	u8         ignore_flow_level[0x1];
502 	u8         reserved_at_16[0x1];
503 	u8         table_miss_action_domain[0x1];
504 	u8         termination_table[0x1];
505 	u8         reformat_and_fwd_to_table[0x1];
506 	u8         reserved_at_1a[0x2];
507 	u8         ipsec_encrypt[0x1];
508 	u8         ipsec_decrypt[0x1];
509 	u8         sw_owner_v2[0x1];
510 	u8         reserved_at_1f[0x1];
511 	u8         termination_table_raw_traffic[0x1];
512 	u8         reserved_at_21[0x1];
513 	u8         log_max_ft_size[0x6];
514 	u8         log_max_modify_header_context[0x8];
515         u8         max_modify_header_actions[0x8];
516 	u8         max_ft_level[0x8];
517 
518 	u8         reformat_add_esp_trasport[0x1];
519 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
520 	u8         reformat_add_esp_transport_over_udp[0x1];
521 	u8         reformat_del_esp_trasport[0x1];
522 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
523 	u8         reformat_del_esp_transport_over_udp[0x1];
524 	u8         execute_aso[0x1];
525 	u8         reserved_at_47[0x19];
526 	u8         reserved_at_60[0x2];
527 	u8         reformat_insert[0x1];
528 	u8         reformat_remove[0x1];
529 	u8         macsec_encrypt[0x1];
530 	u8         macsec_decrypt[0x1];
531 	u8         reserved_at_66[0x2];
532 	u8         reformat_add_macsec[0x1];
533 	u8         reformat_remove_macsec[0x1];
534 	u8         reserved_at_6a[0xe];
535 	u8         log_max_ft_num[0x8];
536 	u8         reserved_at_80[0x10];
537 	u8         log_max_flow_counter[0x8];
538 	u8         log_max_destination[0x8];
539 	u8         reserved_at_a0[0x18];
540 	u8         log_max_flow[0x8];
541 	u8         reserved_at_c0[0x40];
542 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
543 
544 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
545 };
546 
547 struct mlx5_ifc_odp_per_transport_service_cap_bits {
548 	u8         send[0x1];
549 	u8         receive[0x1];
550 	u8         write[0x1];
551 	u8         read[0x1];
552 	u8         atomic[0x1];
553 	u8         srq_receive[0x1];
554 	u8         reserved_0[0x1a];
555 };
556 
557 struct mlx5_ifc_flow_counter_list_bits {
558 	u8         reserved_0[0x10];
559 	u8         flow_counter_id[0x10];
560 
561 	u8         reserved_1[0x20];
562 };
563 
564 struct mlx5_ifc_dest_format_struct_bits {
565         u8         destination_type[0x8];
566         u8         destination_id[0x18];
567 
568         u8         destination_eswitch_owner_vhca_id_valid[0x1];
569         u8         packet_reformat[0x1];
570         u8         reserved_at_22[0x6];
571         u8         destination_table_type[0x8];
572         u8         destination_eswitch_owner_vhca_id[0x10];
573 };
574 
575 struct mlx5_ifc_ipv4_layout_bits {
576 	u8         reserved_at_0[0x60];
577 
578 	u8         ipv4[0x20];
579 };
580 
581 struct mlx5_ifc_ipv6_layout_bits {
582 	u8         ipv6[16][0x8];
583 };
584 
585 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
586 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
587 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
588 	u8         reserved_at_0[0x80];
589 };
590 
591 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
592 	u8         smac_47_16[0x20];
593 
594 	u8         smac_15_0[0x10];
595 	u8         ethertype[0x10];
596 
597 	u8         dmac_47_16[0x20];
598 
599 	u8         dmac_15_0[0x10];
600 	u8         first_prio[0x3];
601 	u8         first_cfi[0x1];
602 	u8         first_vid[0xc];
603 
604 	u8         ip_protocol[0x8];
605 	u8         ip_dscp[0x6];
606 	u8         ip_ecn[0x2];
607 	u8         cvlan_tag[0x1];
608 	u8         svlan_tag[0x1];
609 	u8         frag[0x1];
610 	u8         ip_version[0x4];
611 	u8         tcp_flags[0x9];
612 
613 	u8         tcp_sport[0x10];
614 	u8         tcp_dport[0x10];
615 
616 	u8         reserved_2[0x20];
617 
618 	u8         udp_sport[0x10];
619 	u8         udp_dport[0x10];
620 
621 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
622 
623 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
624 };
625 
626 struct mlx5_ifc_nvgre_key_bits {
627 	u8 hi[0x18];
628 	u8 lo[0x8];
629 };
630 
631 union mlx5_ifc_gre_key_bits {
632 	struct mlx5_ifc_nvgre_key_bits nvgre;
633 	u8 key[0x20];
634 };
635 
636 struct mlx5_ifc_fte_match_set_misc_bits {
637 	u8         gre_c_present[0x1];
638 	u8         reserved_at_1[0x1];
639 	u8         gre_k_present[0x1];
640 	u8         gre_s_present[0x1];
641 	u8         source_vhca_port[0x4];
642 	u8         source_sqn[0x18];
643 
644 	u8         source_eswitch_owner_vhca_id[0x10];
645 	u8         source_port[0x10];
646 
647 	u8         outer_second_prio[0x3];
648 	u8         outer_second_cfi[0x1];
649 	u8         outer_second_vid[0xc];
650 	u8         inner_second_prio[0x3];
651 	u8         inner_second_cfi[0x1];
652 	u8         inner_second_vid[0xc];
653 
654 	u8         outer_second_cvlan_tag[0x1];
655 	u8         inner_second_cvlan_tag[0x1];
656 	u8         outer_second_svlan_tag[0x1];
657 	u8         inner_second_svlan_tag[0x1];
658 	u8         reserved_at_64[0xc];
659 	u8         gre_protocol[0x10];
660 
661 	union mlx5_ifc_gre_key_bits gre_key;
662 
663 	u8         vxlan_vni[0x18];
664 	u8         bth_opcode[0x8];
665 
666 	u8         geneve_vni[0x18];
667 	u8         reserved_at_d8[0x6];
668 	u8         geneve_tlv_option_0_exist[0x1];
669 	u8         geneve_oam[0x1];
670 
671 	u8         reserved_at_e0[0xc];
672 	u8         outer_ipv6_flow_label[0x14];
673 
674 	u8         reserved_at_100[0xc];
675 	u8         inner_ipv6_flow_label[0x14];
676 
677 	u8         reserved_at_120[0xa];
678 	u8         geneve_opt_len[0x6];
679 	u8         geneve_protocol_type[0x10];
680 
681 	u8         reserved_at_140[0x8];
682 	u8         bth_dst_qp[0x18];
683 	u8         inner_esp_spi[0x20];
684 	u8         outer_esp_spi[0x20];
685 	u8         reserved_at_1a0[0x60];
686 };
687 
688 struct mlx5_ifc_fte_match_mpls_bits {
689 	u8         mpls_label[0x14];
690 	u8         mpls_exp[0x3];
691 	u8         mpls_s_bos[0x1];
692 	u8         mpls_ttl[0x8];
693 };
694 
695 struct mlx5_ifc_fte_match_set_misc2_bits {
696 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
697 
698 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
699 
700 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
701 
702 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
703 
704 	u8         metadata_reg_c_7[0x20];
705 
706 	u8         metadata_reg_c_6[0x20];
707 
708 	u8         metadata_reg_c_5[0x20];
709 
710 	u8         metadata_reg_c_4[0x20];
711 
712 	u8         metadata_reg_c_3[0x20];
713 
714 	u8         metadata_reg_c_2[0x20];
715 
716 	u8         metadata_reg_c_1[0x20];
717 
718 	u8         metadata_reg_c_0[0x20];
719 
720 	u8         metadata_reg_a[0x20];
721 
722 	u8         reserved_at_1a0[0x8];
723 
724 	u8         macsec_syndrome[0x8];
725 	u8         ipsec_syndrome[0x8];
726 	u8         reserved_at_1b8[0x8];
727 
728 	u8         reserved_at_1c0[0x40];
729 };
730 
731 struct mlx5_ifc_fte_match_set_misc3_bits {
732 	u8         inner_tcp_seq_num[0x20];
733 
734 	u8         outer_tcp_seq_num[0x20];
735 
736 	u8         inner_tcp_ack_num[0x20];
737 
738 	u8         outer_tcp_ack_num[0x20];
739 
740 	u8         reserved_at_80[0x8];
741 	u8         outer_vxlan_gpe_vni[0x18];
742 
743 	u8         outer_vxlan_gpe_next_protocol[0x8];
744 	u8         outer_vxlan_gpe_flags[0x8];
745 	u8         reserved_at_b0[0x10];
746 
747 	u8         icmp_header_data[0x20];
748 
749 	u8         icmpv6_header_data[0x20];
750 
751 	u8         icmp_type[0x8];
752 	u8         icmp_code[0x8];
753 	u8         icmpv6_type[0x8];
754 	u8         icmpv6_code[0x8];
755 
756 	u8         geneve_tlv_option_0_data[0x20];
757 
758 	u8         gtpu_teid[0x20];
759 
760 	u8         gtpu_msg_type[0x8];
761 	u8         gtpu_msg_flags[0x8];
762 	u8         reserved_at_170[0x10];
763 
764 	u8         gtpu_dw_2[0x20];
765 
766 	u8         gtpu_first_ext_dw_0[0x20];
767 
768 	u8         gtpu_dw_0[0x20];
769 
770 	u8         reserved_at_1e0[0x20];
771 };
772 
773 struct mlx5_ifc_fte_match_set_misc4_bits {
774         u8         prog_sample_field_value_0[0x20];
775 
776         u8         prog_sample_field_id_0[0x20];
777 
778         u8         prog_sample_field_value_1[0x20];
779 
780         u8         prog_sample_field_id_1[0x20];
781 
782         u8         prog_sample_field_value_2[0x20];
783 
784         u8         prog_sample_field_id_2[0x20];
785 
786         u8         prog_sample_field_value_3[0x20];
787 
788         u8         prog_sample_field_id_3[0x20];
789 
790         u8         reserved_at_100[0x100];
791 };
792 
793 struct mlx5_ifc_fte_match_set_misc5_bits {
794         u8         macsec_tag_0[0x20];
795 
796         u8         macsec_tag_1[0x20];
797 
798         u8         macsec_tag_2[0x20];
799 
800         u8         macsec_tag_3[0x20];
801 
802         u8         tunnel_header_0[0x20];
803 
804         u8         tunnel_header_1[0x20];
805 
806         u8         tunnel_header_2[0x20];
807 
808         u8         tunnel_header_3[0x20];
809 
810         u8         reserved_at_100[0x100];
811 };
812 
813 struct mlx5_ifc_cmd_pas_bits {
814 	u8         pa_h[0x20];
815 
816 	u8         pa_l[0x14];
817 	u8         reserved_0[0xc];
818 };
819 
820 struct mlx5_ifc_uint64_bits {
821 	u8         hi[0x20];
822 
823 	u8         lo[0x20];
824 };
825 
826 struct mlx5_ifc_application_prio_entry_bits {
827 	u8         reserved_0[0x8];
828 	u8         priority[0x3];
829 	u8         reserved_1[0x2];
830 	u8         sel[0x3];
831 	u8         protocol_id[0x10];
832 };
833 
834 struct mlx5_ifc_nodnic_ring_doorbell_bits {
835 	u8         reserved_0[0x8];
836 	u8         ring_pi[0x10];
837 	u8         reserved_1[0x8];
838 };
839 
840 enum {
841 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
842 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
843 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
844 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
845 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
846 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
847 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
848 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
849 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
850 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
851 };
852 
853 struct mlx5_ifc_ads_bits {
854 	u8         fl[0x1];
855 	u8         free_ar[0x1];
856 	u8         reserved_0[0xe];
857 	u8         pkey_index[0x10];
858 
859 	u8         reserved_1[0x8];
860 	u8         grh[0x1];
861 	u8         mlid[0x7];
862 	u8         rlid[0x10];
863 
864 	u8         ack_timeout[0x5];
865 	u8         reserved_2[0x3];
866 	u8         src_addr_index[0x8];
867 	u8         log_rtm[0x4];
868 	u8         stat_rate[0x4];
869 	u8         hop_limit[0x8];
870 
871 	u8         reserved_3[0x4];
872 	u8         tclass[0x8];
873 	u8         flow_label[0x14];
874 
875 	u8         rgid_rip[16][0x8];
876 
877 	u8         reserved_4[0x4];
878 	u8         f_dscp[0x1];
879 	u8         f_ecn[0x1];
880 	u8         reserved_5[0x1];
881 	u8         f_eth_prio[0x1];
882 	u8         ecn[0x2];
883 	u8         dscp[0x6];
884 	u8         udp_sport[0x10];
885 
886 	u8         dei_cfi[0x1];
887 	u8         eth_prio[0x3];
888 	u8         sl[0x4];
889 	u8         port[0x8];
890 	u8         rmac_47_32[0x10];
891 
892 	u8         rmac_31_0[0x20];
893 };
894 
895 struct mlx5_ifc_diagnostic_counter_cap_bits {
896 	u8         sync[0x1];
897 	u8         reserved_0[0xf];
898 	u8         counter_id[0x10];
899 };
900 
901 struct mlx5_ifc_debug_cap_bits {
902 	u8         reserved_0[0x18];
903 	u8         log_max_samples[0x8];
904 
905 	u8         single[0x1];
906 	u8         repetitive[0x1];
907 	u8         health_mon_rx_activity[0x1];
908 	u8         reserved_1[0x15];
909 	u8         log_min_sample_period[0x8];
910 
911 	u8         reserved_2[0x1c0];
912 
913 	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
914 };
915 
916 struct mlx5_ifc_qos_cap_bits {
917 	u8         packet_pacing[0x1];
918 	u8         esw_scheduling[0x1];
919 	u8         esw_bw_share[0x1];
920 	u8         esw_rate_limit[0x1];
921 	u8         hll[0x1];
922 	u8         packet_pacing_burst_bound[0x1];
923 	u8         packet_pacing_typical_size[0x1];
924 	u8         reserved_at_7[0x19];
925 
926 	u8 	   reserved_at_20[0xA];
927 	u8	   qos_remap_pp[0x1];
928 	u8         reserved_at_2b[0x15];
929 
930 	u8         packet_pacing_max_rate[0x20];
931 
932 	u8         packet_pacing_min_rate[0x20];
933 
934 	u8         reserved_at_80[0x10];
935 	u8         packet_pacing_rate_table_size[0x10];
936 
937 	u8         esw_element_type[0x10];
938 	u8         esw_tsar_type[0x10];
939 
940 	u8         reserved_at_c0[0x10];
941 	u8         max_qos_para_vport[0x10];
942 
943 	u8         max_tsar_bw_share[0x20];
944 
945 	u8         reserved_at_100[0x700];
946 };
947 
948 struct mlx5_ifc_snapshot_cap_bits {
949 	u8         reserved_0[0x1d];
950 	u8         suspend_qp_uc[0x1];
951 	u8         suspend_qp_ud[0x1];
952 	u8         suspend_qp_rc[0x1];
953 
954 	u8         reserved_1[0x1c];
955 	u8         restore_pd[0x1];
956 	u8         restore_uar[0x1];
957 	u8         restore_mkey[0x1];
958 	u8         restore_qp[0x1];
959 
960 	u8         reserved_2[0x1e];
961 	u8         named_mkey[0x1];
962 	u8         named_qp[0x1];
963 
964 	u8         reserved_3[0x7a0];
965 };
966 
967 struct mlx5_ifc_e_switch_cap_bits {
968         u8         vport_svlan_strip[0x1];
969         u8         vport_cvlan_strip[0x1];
970         u8         vport_svlan_insert[0x1];
971         u8         vport_cvlan_insert_if_not_exist[0x1];
972         u8         vport_cvlan_insert_overwrite[0x1];
973         u8         reserved_at_5[0x1];
974         u8         vport_cvlan_insert_always[0x1];
975         u8         esw_shared_ingress_acl[0x1];
976         u8         esw_uplink_ingress_acl[0x1];
977         u8         root_ft_on_other_esw[0x1];
978         u8         reserved_at_a[0xf];
979         u8         esw_functions_changed[0x1];
980         u8         reserved_at_1a[0x1];
981         u8         ecpf_vport_exists[0x1];
982         u8         counter_eswitch_affinity[0x1];
983         u8         merged_eswitch[0x1];
984         u8         nic_vport_node_guid_modify[0x1];
985         u8         nic_vport_port_guid_modify[0x1];
986 
987         u8         vxlan_encap_decap[0x1];
988         u8         nvgre_encap_decap[0x1];
989         u8         reserved_at_22[0x1];
990         u8         log_max_fdb_encap_uplink[0x5];
991         u8         reserved_at_21[0x3];
992         u8         log_max_packet_reformat_context[0x5];
993         u8         reserved_2b[0x6];
994         u8         max_encap_header_size[0xa];
995 
996         u8         reserved_at_40[0xb];
997         u8         log_max_esw_sf[0x5];
998         u8         esw_sf_base_id[0x10];
999 
1000         u8         reserved_at_60[0x7a0];
1001 
1002 };
1003 
1004 struct mlx5_ifc_flow_table_eswitch_cap_bits {
1005 	u8         reserved_0[0x200];
1006 
1007 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
1008 
1009 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
1010 
1011 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
1012 
1013 	u8         reserved_1[0x7800];
1014 };
1015 
1016 struct mlx5_ifc_flow_table_nic_cap_bits {
1017 	u8         nic_rx_multi_path_tirs[0x1];
1018         u8         nic_rx_multi_path_tirs_fts[0x1];
1019         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
1020         u8         reserved_at_3[0x4];
1021         u8         sw_owner_reformat_supported[0x1];
1022         u8         reserved_at_8[0x18];
1023 
1024         u8         encap_general_header[0x1];
1025         u8         reserved_at_21[0xa];
1026         u8         log_max_packet_reformat_context[0x5];
1027         u8         reserved_at_30[0x6];
1028         u8         max_encap_header_size[0xa];
1029         u8         reserved_at_40[0x1c0];
1030 
1031 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
1032 
1033 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
1034 
1035 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
1036 
1037 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
1038 
1039 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
1040 
1041 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
1042 
1043 	u8         reserved_1[0x7200];
1044 };
1045 
1046 struct mlx5_ifc_port_selection_cap_bits {
1047         u8         reserved_at_0[0x10];
1048         u8         port_select_flow_table[0x1];
1049         u8         reserved_at_11[0x1];
1050         u8         port_select_flow_table_bypass[0x1];
1051         u8         reserved_at_13[0xd];
1052 
1053         u8         reserved_at_20[0x1e0];
1054 
1055         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
1056 
1057         u8         reserved_at_400[0x7c00];
1058 };
1059 
1060 struct mlx5_ifc_pddr_module_info_bits {
1061 	u8         cable_technology[0x8];
1062 	u8         cable_breakout[0x8];
1063 	u8         ext_ethernet_compliance_code[0x8];
1064 	u8         ethernet_compliance_code[0x8];
1065 
1066 	u8         cable_type[0x4];
1067 	u8         cable_vendor[0x4];
1068 	u8         cable_length[0x8];
1069 	u8         cable_identifier[0x8];
1070 	u8         cable_power_class[0x8];
1071 
1072 	u8         reserved_at_40[0x8];
1073 	u8         cable_rx_amp[0x8];
1074 	u8         cable_rx_emphasis[0x8];
1075 	u8         cable_tx_equalization[0x8];
1076 
1077 	u8         reserved_at_60[0x8];
1078 	u8         cable_attenuation_12g[0x8];
1079 	u8         cable_attenuation_7g[0x8];
1080 	u8         cable_attenuation_5g[0x8];
1081 
1082 	u8         reserved_at_80[0x8];
1083 	u8         rx_cdr_cap[0x4];
1084 	u8         tx_cdr_cap[0x4];
1085 	u8         reserved_at_90[0x4];
1086 	u8         rx_cdr_state[0x4];
1087 	u8         reserved_at_98[0x4];
1088 	u8         tx_cdr_state[0x4];
1089 
1090 	u8         vendor_name[16][0x8];
1091 
1092 	u8         vendor_pn[16][0x8];
1093 
1094 	u8         vendor_rev[0x20];
1095 
1096 	u8         fw_version[0x20];
1097 
1098 	u8         vendor_sn[16][0x8];
1099 
1100 	u8         temperature[0x10];
1101 	u8         voltage[0x10];
1102 
1103 	u8         rx_power_lane0[0x10];
1104 	u8         rx_power_lane1[0x10];
1105 
1106 	u8         rx_power_lane2[0x10];
1107 	u8         rx_power_lane3[0x10];
1108 
1109 	u8         reserved_at_2c0[0x40];
1110 
1111 	u8         tx_power_lane0[0x10];
1112 	u8         tx_power_lane1[0x10];
1113 
1114 	u8         tx_power_lane2[0x10];
1115 	u8         tx_power_lane3[0x10];
1116 
1117 	u8         reserved_at_340[0x40];
1118 
1119 	u8         tx_bias_lane0[0x10];
1120 	u8         tx_bias_lane1[0x10];
1121 
1122 	u8         tx_bias_lane2[0x10];
1123 	u8         tx_bias_lane3[0x10];
1124 
1125 	u8         reserved_at_3c0[0x40];
1126 
1127 	u8         temperature_high_th[0x10];
1128 	u8         temperature_low_th[0x10];
1129 
1130 	u8         voltage_high_th[0x10];
1131 	u8         voltage_low_th[0x10];
1132 
1133 	u8         rx_power_high_th[0x10];
1134 	u8         rx_power_low_th[0x10];
1135 
1136 	u8         tx_power_high_th[0x10];
1137 	u8         tx_power_low_th[0x10];
1138 
1139 	u8         tx_bias_high_th[0x10];
1140 	u8         tx_bias_low_th[0x10];
1141 
1142 	u8         reserved_at_4a0[0x10];
1143 	u8         wavelength[0x10];
1144 
1145 	u8         reserved_at_4c0[0x300];
1146 };
1147 
1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1149 	u8         csum_cap[0x1];
1150 	u8         vlan_cap[0x1];
1151 	u8         lro_cap[0x1];
1152 	u8         lro_psh_flag[0x1];
1153 	u8         lro_time_stamp[0x1];
1154 	u8         lro_max_msg_sz_mode[0x2];
1155 	u8         wqe_vlan_insert[0x1];
1156 	u8         self_lb_en_modifiable[0x1];
1157 	u8         self_lb_mc[0x1];
1158 	u8         self_lb_uc[0x1];
1159 	u8         max_lso_cap[0x5];
1160 	u8         multi_pkt_send_wqe[0x2];
1161 	u8         wqe_inline_mode[0x2];
1162 	u8         rss_ind_tbl_cap[0x4];
1163 	u8	   reg_umr_sq[0x1];
1164 	u8         scatter_fcs[0x1];
1165 	u8	   enhanced_multi_pkt_send_wqe[0x1];
1166 	u8         tunnel_lso_const_out_ip_id[0x1];
1167 	u8         tunnel_lro_gre[0x1];
1168 	u8         tunnel_lro_vxlan[0x1];
1169 	u8         tunnel_statless_gre[0x1];
1170 	u8         tunnel_stateless_vxlan[0x1];
1171 
1172 	u8         swp[0x1];
1173 	u8         swp_csum[0x1];
1174 	u8         swp_lso[0x1];
1175 	u8         reserved_2[0x1b];
1176 	u8         max_geneve_opt_len[0x1];
1177 	u8         tunnel_stateless_geneve_rx[0x1];
1178 
1179 	u8         reserved_3[0x10];
1180 	u8         lro_min_mss_size[0x10];
1181 
1182 	u8         reserved_4[0x120];
1183 
1184 	u8         lro_timer_supported_periods[4][0x20];
1185 
1186 	u8         reserved_5[0x600];
1187 };
1188 
1189 enum {
1190 	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
1191 	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
1192 	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
1193 };
1194 
1195 enum {
1196 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1197 	MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1198 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1199 };
1200 
1201 struct mlx5_ifc_roce_cap_bits {
1202 	u8         roce_apm[0x1];
1203 	u8         rts2rts_primary_eth_prio[0x1];
1204 	u8         roce_rx_allow_untagged[0x1];
1205 	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
1206 	u8         reserved_at_4[0x1a];
1207 	u8         qp_ts_format[0x2];
1208 
1209 	u8         reserved_1[0x60];
1210 
1211 	u8         reserved_2[0xc];
1212 	u8         l3_type[0x4];
1213 	u8         reserved_3[0x8];
1214 	u8         roce_version[0x8];
1215 
1216 	u8         reserved_4[0x10];
1217 	u8         r_roce_dest_udp_port[0x10];
1218 
1219 	u8         r_roce_max_src_udp_port[0x10];
1220 	u8         r_roce_min_src_udp_port[0x10];
1221 
1222 	u8         reserved_5[0x10];
1223 	u8         roce_address_table_size[0x10];
1224 
1225 	u8         reserved_6[0x700];
1226 };
1227 
1228 struct mlx5_ifc_device_event_cap_bits {
1229 	u8         user_affiliated_events[4][0x40];
1230 
1231 	u8         user_unaffiliated_events[4][0x40];
1232 };
1233 
1234 enum {
1235 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
1236 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1237 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1238 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1239 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1240 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1241 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1242 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1243 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1244 };
1245 
1246 enum {
1247 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1248 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1249 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1250 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1251 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1252 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1253 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1254 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1255 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1256 };
1257 
1258 struct mlx5_ifc_atomic_caps_bits {
1259 	u8         reserved_0[0x40];
1260 
1261 	u8         atomic_req_8B_endianess_mode[0x2];
1262 	u8         reserved_1[0x4];
1263 	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
1264 
1265 	u8         reserved_2[0x19];
1266 
1267 	u8         reserved_3[0x20];
1268 
1269 	u8         reserved_4[0x10];
1270 	u8         atomic_operations[0x10];
1271 
1272 	u8         reserved_5[0x10];
1273 	u8         atomic_size_qp[0x10];
1274 
1275 	u8         reserved_6[0x10];
1276 	u8         atomic_size_dc[0x10];
1277 
1278 	u8         reserved_7[0x720];
1279 };
1280 
1281 struct mlx5_ifc_odp_cap_bits {
1282 	u8         reserved_0[0x40];
1283 
1284 	u8         sig[0x1];
1285 	u8         reserved_1[0x1f];
1286 
1287 	u8         reserved_2[0x20];
1288 
1289 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1290 
1291 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1292 
1293 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1294 
1295 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1296 
1297 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1298 
1299 	u8         reserved_3[0x6e0];
1300 };
1301 
1302 enum {
1303 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1304 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1305 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1306 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1307 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1308 };
1309 
1310 enum {
1311 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1312 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1313 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1314 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1315 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1316 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1317 };
1318 
1319 enum {
1320 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1321 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1322 };
1323 
1324 enum {
1325 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1326 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1327 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1328 };
1329 
1330 enum {
1331 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1332 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1333 };
1334 
1335 enum {
1336 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1337 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1338 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1339 };
1340 
1341 enum {
1342 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1343 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1344 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1345 };
1346 
1347 struct mlx5_ifc_cmd_hca_cap_bits {
1348 	u8         reserved_0[0x20];
1349 
1350 	u8         hca_cap_2[0x1];
1351 	u8         create_lag_when_not_master_up[0x1];
1352         u8         dtor[0x1];
1353         u8         event_on_vhca_state_teardown_request[0x1];
1354         u8         event_on_vhca_state_in_use[0x1];
1355         u8         event_on_vhca_state_active[0x1];
1356         u8         event_on_vhca_state_allocated[0x1];
1357         u8         event_on_vhca_state_invalid[0x1];
1358         u8         reserved_at_28[0x8];
1359         u8         vhca_id[0x10];
1360 
1361 	u8         reserved_at_40[0x40];
1362 
1363 	u8         log_max_srq_sz[0x8];
1364 	u8         log_max_qp_sz[0x8];
1365 	u8         event_cap[0x1];
1366 	u8         reserved_1[0xa];
1367 	u8         log_max_qp[0x5];
1368 
1369 	u8         reserved_2[0xb];
1370 	u8         log_max_srq[0x5];
1371 	u8         reserved_3[0x10];
1372 
1373 	u8         reserved_4[0x8];
1374 	u8         log_max_cq_sz[0x8];
1375 	u8         relaxed_ordering_write_umr[0x1];
1376 	u8         relaxed_ordering_read_umr[0x1];
1377 	u8         reserved_5[0x9];
1378 	u8         log_max_cq[0x5];
1379 
1380 	u8         log_max_eq_sz[0x8];
1381 	u8         relaxed_ordering_write[0x1];
1382 	u8         relaxed_ordering_read[0x1];
1383 	u8         log_max_mkey[0x6];
1384 	u8         reserved_7[0xb];
1385 	u8         fast_teardown[0x1];
1386 	u8         log_max_eq[0x4];
1387 
1388 	u8         max_indirection[0x8];
1389 	u8         reserved_8[0x1];
1390 	u8         log_max_mrw_sz[0x7];
1391 	u8	   force_teardown[0x1];
1392 	u8         reserved_9[0x1];
1393 	u8         log_max_bsf_list_size[0x6];
1394 	u8         reserved_10[0x2];
1395 	u8         log_max_klm_list_size[0x6];
1396 
1397 	u8         reserved_11[0xa];
1398 	u8         log_max_ra_req_dc[0x6];
1399 	u8         reserved_12[0xa];
1400 	u8         log_max_ra_res_dc[0x6];
1401 
1402 	u8         reserved_13[0xa];
1403 	u8         log_max_ra_req_qp[0x6];
1404 	u8         reserved_14[0xa];
1405 	u8         log_max_ra_res_qp[0x6];
1406 
1407 	u8         pad_cap[0x1];
1408 	u8         cc_query_allowed[0x1];
1409 	u8         cc_modify_allowed[0x1];
1410 	u8         start_pad[0x1];
1411 	u8         cache_line_128byte[0x1];
1412 	u8         reserved_at_165[0xa];
1413 	u8         qcam_reg[0x1];
1414 	u8         gid_table_size[0x10];
1415 
1416 	u8         out_of_seq_cnt[0x1];
1417 	u8         vport_counters[0x1];
1418 	u8         retransmission_q_counters[0x1];
1419 	u8         debug[0x1];
1420 	u8         modify_rq_counters_set_id[0x1];
1421 	u8         rq_delay_drop[0x1];
1422 	u8         max_qp_cnt[0xa];
1423 	u8         pkey_table_size[0x10];
1424 
1425 	u8         vport_group_manager[0x1];
1426 	u8         vhca_group_manager[0x1];
1427 	u8         ib_virt[0x1];
1428 	u8         eth_virt[0x1];
1429 	u8         reserved_17[0x1];
1430 	u8         ets[0x1];
1431 	u8         nic_flow_table[0x1];
1432 	u8         eswitch_flow_table[0x1];
1433 	u8         reserved_18[0x1];
1434 	u8         mcam_reg[0x1];
1435 	u8         pcam_reg[0x1];
1436 	u8         local_ca_ack_delay[0x5];
1437 	u8         port_module_event[0x1];
1438 	u8         reserved_19[0x5];
1439 	u8         port_type[0x2];
1440 	u8         num_ports[0x8];
1441 
1442 	u8         snapshot[0x1];
1443 	u8         reserved_20[0x2];
1444 	u8         log_max_msg[0x5];
1445 	u8         reserved_21[0x4];
1446 	u8         max_tc[0x4];
1447 	u8         temp_warn_event[0x1];
1448 	u8         dcbx[0x1];
1449 	u8         general_notification_event[0x1];
1450 	u8         reserved_at_1d3[0x2];
1451 	u8         fpga[0x1];
1452 	u8         rol_s[0x1];
1453 	u8         rol_g[0x1];
1454 	u8         reserved_23[0x1];
1455 	u8         wol_s[0x1];
1456 	u8         wol_g[0x1];
1457 	u8         wol_a[0x1];
1458 	u8         wol_b[0x1];
1459 	u8         wol_m[0x1];
1460 	u8         wol_u[0x1];
1461 	u8         wol_p[0x1];
1462 
1463 	u8         stat_rate_support[0x10];
1464 	u8         reserved_24[0xc];
1465 	u8         cqe_version[0x4];
1466 
1467 	u8         compact_address_vector[0x1];
1468 	u8         striding_rq[0x1];
1469 	u8         reserved_25[0x1];
1470 	u8         ipoib_enhanced_offloads[0x1];
1471 	u8         ipoib_ipoib_offloads[0x1];
1472 	u8         reserved_26[0x8];
1473 	u8         dc_connect_qp[0x1];
1474 	u8         dc_cnak_trace[0x1];
1475 	u8         drain_sigerr[0x1];
1476 	u8         cmdif_checksum[0x2];
1477 	u8         sigerr_cqe[0x1];
1478 	u8         reserved_27[0x1];
1479 	u8         wq_signature[0x1];
1480 	u8         sctr_data_cqe[0x1];
1481 	u8         reserved_28[0x1];
1482 	u8         sho[0x1];
1483 	u8         tph[0x1];
1484 	u8         rf[0x1];
1485 	u8         dct[0x1];
1486 	u8         qos[0x1];
1487 	u8         eth_net_offloads[0x1];
1488 	u8         roce[0x1];
1489 	u8         atomic[0x1];
1490 	u8         reserved_30[0x1];
1491 
1492 	u8         cq_oi[0x1];
1493 	u8         cq_resize[0x1];
1494 	u8         cq_moderation[0x1];
1495 	u8         cq_period_mode_modify[0x1];
1496 	u8         cq_invalidate[0x1];
1497 	u8         reserved_at_225[0x1];
1498 	u8         cq_eq_remap[0x1];
1499 	u8         pg[0x1];
1500 	u8         block_lb_mc[0x1];
1501 	u8         exponential_backoff[0x1];
1502 	u8         scqe_break_moderation[0x1];
1503 	u8         cq_period_start_from_cqe[0x1];
1504 	u8         cd[0x1];
1505 	u8         atm[0x1];
1506 	u8         apm[0x1];
1507 	u8	   imaicl[0x1];
1508 	u8         reserved_32[0x6];
1509 	u8         qkv[0x1];
1510 	u8         pkv[0x1];
1511 	u8	   set_deth_sqpn[0x1];
1512 	u8         reserved_33[0x3];
1513 	u8         xrc[0x1];
1514 	u8         ud[0x1];
1515 	u8         uc[0x1];
1516 	u8         rc[0x1];
1517 
1518 	u8         uar_4k[0x1];
1519 	u8         reserved_at_241[0x9];
1520 	u8         uar_sz[0x6];
1521 	u8         reserved_35[0x8];
1522 	u8         log_pg_sz[0x8];
1523 
1524 	u8         bf[0x1];
1525 	u8         driver_version[0x1];
1526 	u8         pad_tx_eth_packet[0x1];
1527 	u8         reserved_36[0x8];
1528 	u8         log_bf_reg_size[0x5];
1529 	u8         reserved_37[0x10];
1530 
1531 	u8         num_of_diagnostic_counters[0x10];
1532 	u8         max_wqe_sz_sq[0x10];
1533 
1534 	u8         reserved_38[0x10];
1535 	u8         max_wqe_sz_rq[0x10];
1536 
1537 	u8         reserved_39[0x10];
1538 	u8         max_wqe_sz_sq_dc[0x10];
1539 
1540 	u8         reserved_40[0x7];
1541 	u8         max_qp_mcg[0x19];
1542 
1543 	u8         reserved_41[0x10];
1544 	u8         flow_counter_bulk_alloc[0x8];
1545 	u8         log_max_mcg[0x8];
1546 
1547 	u8         reserved_42[0x3];
1548 	u8         log_max_transport_domain[0x5];
1549 	u8         reserved_43[0x3];
1550 	u8         log_max_pd[0x5];
1551 	u8         reserved_44[0xb];
1552 	u8         log_max_xrcd[0x5];
1553 
1554 	u8         nic_receive_steering_discard[0x1];
1555 	u8	   reserved_45[0x7];
1556 	u8         log_max_flow_counter_bulk[0x8];
1557 	u8         max_flow_counter[0x10];
1558 
1559 	u8         reserved_46[0x3];
1560 	u8         log_max_rq[0x5];
1561 	u8         reserved_47[0x3];
1562 	u8         log_max_sq[0x5];
1563 	u8         reserved_48[0x3];
1564 	u8         log_max_tir[0x5];
1565 	u8         reserved_49[0x3];
1566 	u8         log_max_tis[0x5];
1567 
1568 	u8         basic_cyclic_rcv_wqe[0x1];
1569 	u8         reserved_50[0x2];
1570 	u8         log_max_rmp[0x5];
1571 	u8         reserved_51[0x3];
1572 	u8         log_max_rqt[0x5];
1573 	u8         reserved_52[0x3];
1574 	u8         log_max_rqt_size[0x5];
1575 	u8         reserved_53[0x3];
1576 	u8         log_max_tis_per_sq[0x5];
1577 
1578 	u8         reserved_54[0x3];
1579 	u8         log_max_stride_sz_rq[0x5];
1580 	u8         reserved_55[0x3];
1581 	u8         log_min_stride_sz_rq[0x5];
1582 	u8         reserved_56[0x3];
1583 	u8         log_max_stride_sz_sq[0x5];
1584 	u8         reserved_57[0x3];
1585 	u8         log_min_stride_sz_sq[0x5];
1586 
1587 	u8         reserved_58[0x1b];
1588 	u8         log_max_wq_sz[0x5];
1589 
1590 	u8         nic_vport_change_event[0x1];
1591 	u8         disable_local_lb_uc[0x1];
1592 	u8         disable_local_lb_mc[0x1];
1593 	u8         reserved_59[0x8];
1594 	u8         log_max_vlan_list[0x5];
1595 	u8         reserved_60[0x3];
1596 	u8         log_max_current_mc_list[0x5];
1597 	u8         reserved_61[0x3];
1598 	u8         log_max_current_uc_list[0x5];
1599 
1600 	u8         general_obj_types[0x40];
1601 
1602 	u8         sq_ts_format[0x2];
1603 	u8         rq_ts_format[0x2];
1604 	u8         reserved_at_444[0x4];
1605 	u8         create_qp_start_hint[0x18];
1606 
1607 	u8         reserved_at_460[0x3];
1608 	u8         log_max_uctx[0x5];
1609 	u8         reserved_at_468[0x2];
1610 	u8         ipsec_offload[0x1];
1611 	u8         log_max_umem[0x5];
1612 	u8         max_num_eqs[0x10];
1613 
1614 	u8         reserved_at_480[0x1];
1615 	u8         tls_tx[0x1];
1616 	u8         tls_rx[0x1];
1617 	u8         log_max_l2_table[0x5];
1618 	u8         reserved_64[0x8];
1619 	u8         log_uar_page_sz[0x10];
1620 
1621 	u8         reserved_65[0x20];
1622 
1623 	u8         device_frequency_mhz[0x20];
1624 
1625 	u8         device_frequency_khz[0x20];
1626 
1627 	u8         reserved_at_500[0x20];
1628 	u8	   num_of_uars_per_page[0x20];
1629 	u8         reserved_at_540[0x40];
1630 
1631 	u8         log_max_atomic_size_qp[0x8];
1632 	u8         reserved_67[0x10];
1633 	u8         log_max_atomic_size_dc[0x8];
1634 
1635 	u8         reserved_at_5a0[0x13];
1636 	u8         log_max_dek[0x5];
1637 	u8         reserved_at_5b8[0x4];
1638 	u8         mini_cqe_resp_stride_index[0x1];
1639 	u8         cqe_128_always[0x1];
1640 	u8         cqe_compression_128b[0x1];
1641 
1642 	u8         cqe_compression[0x1];
1643 
1644 	u8         cqe_compression_timeout[0x10];
1645 	u8         cqe_compression_max_num[0x10];
1646 
1647 	u8         reserved_5e0[0xc0];
1648 
1649 	u8         uctx_cap[0x20];
1650 
1651 	u8         reserved_6c0[0xc0];
1652 
1653 	u8	   vhca_tunnel_commands[0x40];
1654 	u8	   reserved_at_7c0[0x40];
1655 };
1656 
1657 struct mlx5_ifc_cmd_hca_cap_2_bits {
1658 	u8	   reserved_at_0[0x80];
1659 
1660 	u8         migratable[0x1];
1661 	u8         reserved_at_81[0x1f];
1662 
1663 	u8	   max_reformat_insert_size[0x8];
1664 	u8	   max_reformat_insert_offset[0x8];
1665 	u8	   max_reformat_remove_size[0x8];
1666 	u8	   max_reformat_remove_offset[0x8];
1667 
1668 	u8	   reserved_at_c0[0x8];
1669 	u8	   migration_multi_load[0x1];
1670 	u8	   migration_tracking_state[0x1];
1671 	u8	   reserved_at_ca[0x16];
1672 
1673 	u8	   reserved_at_e0[0xc0];
1674 
1675 	u8	   flow_table_type_2_type[0x8];
1676 	u8	   reserved_at_1a8[0x3];
1677 	u8	   log_min_mkey_entity_size[0x5];
1678 	u8	   reserved_at_1b0[0x10];
1679 
1680 	u8	   reserved_at_1c0[0x60];
1681 
1682 	u8	   reserved_at_220[0x1];
1683 	u8	   sw_vhca_id_valid[0x1];
1684 	u8	   sw_vhca_id[0xe];
1685 	u8	   reserved_at_230[0x10];
1686 
1687 	u8	   reserved_at_240[0xb];
1688 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
1689 	u8	   reserved_at_250[0x10];
1690 
1691 	u8	   reserved_at_260[0x5a0];
1692 };
1693 
1694 enum mlx5_ifc_flow_destination_type {
1695         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1696         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1697         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1698         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1699         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1700         MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
1701 };
1702 
1703 enum mlx5_flow_table_miss_action {
1704         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1705         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1706         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1707 };
1708 
1709 struct mlx5_ifc_extended_dest_format_bits {
1710         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1711 
1712         u8         packet_reformat_id[0x20];
1713 
1714         u8         reserved_at_60[0x20];
1715 };
1716 
1717 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1718 	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1719 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1720 	u8         reserved_0[0x40];
1721 };
1722 
1723 struct mlx5_ifc_fte_match_param_bits {
1724         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1725 
1726         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1727 
1728         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1729 
1730         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1731 
1732         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1733 
1734         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1735 
1736         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1737 
1738         u8         reserved_at_e00[0x200];
1739 };
1740 
1741 enum {
1742 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1743 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1744 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1745 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1746 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1747 };
1748 
1749 struct mlx5_ifc_rx_hash_field_select_bits {
1750 	u8         l3_prot_type[0x1];
1751 	u8         l4_prot_type[0x1];
1752 	u8         selected_fields[0x1e];
1753 };
1754 
1755 struct mlx5_ifc_tls_capabilities_bits {
1756 	u8         tls_1_2_aes_gcm_128[0x1];
1757 	u8         tls_1_3_aes_gcm_128[0x1];
1758 	u8         tls_1_2_aes_gcm_256[0x1];
1759 	u8         tls_1_3_aes_gcm_256[0x1];
1760 	u8         reserved_at_4[0x1c];
1761 
1762 	u8         reserved_at_20[0x7e0];
1763 };
1764 
1765 enum {
1766 	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1767 	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1768 	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1769 	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1770 };
1771 
1772 enum rq_type {
1773 	RQ_TYPE_NONE,
1774 	RQ_TYPE_STRIDE,
1775 };
1776 
1777 enum {
1778 	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1779 	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1780 };
1781 
1782 struct mlx5_ifc_wq_bits {
1783 	u8         wq_type[0x4];
1784 	u8         wq_signature[0x1];
1785 	u8         end_padding_mode[0x2];
1786 	u8         cd_slave[0x1];
1787 	u8         reserved_0[0x18];
1788 
1789 	u8         hds_skip_first_sge[0x1];
1790 	u8         log2_hds_buf_size[0x3];
1791 	u8         reserved_1[0x7];
1792 	u8         page_offset[0x5];
1793 	u8         lwm[0x10];
1794 
1795 	u8         reserved_2[0x8];
1796 	u8         pd[0x18];
1797 
1798 	u8         reserved_3[0x8];
1799 	u8         uar_page[0x18];
1800 
1801 	u8         dbr_addr[0x40];
1802 
1803 	u8         hw_counter[0x20];
1804 
1805 	u8         sw_counter[0x20];
1806 
1807 	u8         reserved_4[0xc];
1808 	u8         log_wq_stride[0x4];
1809 	u8         reserved_5[0x3];
1810 	u8         log_wq_pg_sz[0x5];
1811 	u8         reserved_6[0x3];
1812 	u8         log_wq_sz[0x5];
1813 
1814 	u8         dbr_umem_valid[0x1];
1815 	u8         wq_umem_valid[0x1];
1816 	u8         reserved_7[0x13];
1817 	u8         single_wqe_log_num_of_strides[0x3];
1818 	u8         two_byte_shift_en[0x1];
1819 	u8         reserved_8[0x4];
1820 	u8         single_stride_log_num_of_bytes[0x3];
1821 
1822 	u8         reserved_9[0x4c0];
1823 
1824 	struct mlx5_ifc_cmd_pas_bits pas[0];
1825 };
1826 
1827 struct mlx5_ifc_rq_num_bits {
1828 	u8         reserved_0[0x8];
1829 	u8         rq_num[0x18];
1830 };
1831 
1832 struct mlx5_ifc_mac_address_layout_bits {
1833 	u8         reserved_0[0x10];
1834 	u8         mac_addr_47_32[0x10];
1835 
1836 	u8         mac_addr_31_0[0x20];
1837 };
1838 
1839 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1840 	u8         reserved_0[0xa0];
1841 
1842 	u8         min_time_between_cnps[0x20];
1843 
1844 	u8         reserved_1[0x12];
1845 	u8         cnp_dscp[0x6];
1846 	u8         reserved_2[0x4];
1847 	u8         cnp_prio_mode[0x1];
1848 	u8         cnp_802p_prio[0x3];
1849 
1850 	u8         reserved_3[0x720];
1851 };
1852 
1853 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1854 	u8         reserved_0[0x60];
1855 
1856 	u8         reserved_1[0x4];
1857 	u8         clamp_tgt_rate[0x1];
1858 	u8         reserved_2[0x3];
1859 	u8         clamp_tgt_rate_after_time_inc[0x1];
1860 	u8         reserved_3[0x17];
1861 
1862 	u8         reserved_4[0x20];
1863 
1864 	u8         rpg_time_reset[0x20];
1865 
1866 	u8         rpg_byte_reset[0x20];
1867 
1868 	u8         rpg_threshold[0x20];
1869 
1870 	u8         rpg_max_rate[0x20];
1871 
1872 	u8         rpg_ai_rate[0x20];
1873 
1874 	u8         rpg_hai_rate[0x20];
1875 
1876 	u8         rpg_gd[0x20];
1877 
1878 	u8         rpg_min_dec_fac[0x20];
1879 
1880 	u8         rpg_min_rate[0x20];
1881 
1882 	u8         reserved_5[0xe0];
1883 
1884 	u8         rate_to_set_on_first_cnp[0x20];
1885 
1886 	u8         dce_tcp_g[0x20];
1887 
1888 	u8         dce_tcp_rtt[0x20];
1889 
1890 	u8         rate_reduce_monitor_period[0x20];
1891 
1892 	u8         reserved_6[0x20];
1893 
1894 	u8         initial_alpha_value[0x20];
1895 
1896 	u8         reserved_7[0x4a0];
1897 };
1898 
1899 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1900 	u8         reserved_0[0x80];
1901 
1902 	u8         rppp_max_rps[0x20];
1903 
1904 	u8         rpg_time_reset[0x20];
1905 
1906 	u8         rpg_byte_reset[0x20];
1907 
1908 	u8         rpg_threshold[0x20];
1909 
1910 	u8         rpg_max_rate[0x20];
1911 
1912 	u8         rpg_ai_rate[0x20];
1913 
1914 	u8         rpg_hai_rate[0x20];
1915 
1916 	u8         rpg_gd[0x20];
1917 
1918 	u8         rpg_min_dec_fac[0x20];
1919 
1920 	u8         rpg_min_rate[0x20];
1921 
1922 	u8         reserved_1[0x640];
1923 };
1924 
1925 enum {
1926 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1927 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1928 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1929 };
1930 
1931 struct mlx5_ifc_resize_field_select_bits {
1932 	u8         resize_field_select[0x20];
1933 };
1934 
1935 enum {
1936 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1937 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1938 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1939 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1940 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1941 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1942 };
1943 
1944 struct mlx5_ifc_modify_field_select_bits {
1945 	u8         modify_field_select[0x20];
1946 };
1947 
1948 struct mlx5_ifc_field_select_r_roce_np_bits {
1949 	u8         field_select_r_roce_np[0x20];
1950 };
1951 
1952 enum {
1953 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1954 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1955 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1956 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1957 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1958 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1959 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1960 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1961 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1962 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1963 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1964 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1965 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1966 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1967 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1968 };
1969 
1970 struct mlx5_ifc_field_select_r_roce_rp_bits {
1971 	u8         field_select_r_roce_rp[0x20];
1972 };
1973 
1974 enum {
1975 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1976 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1977 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1978 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1979 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1980 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1981 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1982 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1983 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1984 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1985 };
1986 
1987 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1988 	u8         field_select_8021qaurp[0x20];
1989 };
1990 
1991 struct mlx5_ifc_pptb_reg_bits {
1992 	u8         reserved_at_0[0x2];
1993 	u8         mm[0x2];
1994 	u8         reserved_at_4[0x4];
1995 	u8         local_port[0x8];
1996 	u8         reserved_at_10[0x6];
1997 	u8         cm[0x1];
1998 	u8         um[0x1];
1999 	u8         pm[0x8];
2000 
2001 	u8         prio_x_buff[0x20];
2002 
2003 	u8         pm_msb[0x8];
2004 	u8         reserved_at_48[0x10];
2005 	u8         ctrl_buff[0x4];
2006 	u8         untagged_buff[0x4];
2007 };
2008 
2009 struct mlx5_ifc_dcbx_app_reg_bits {
2010 	u8         reserved_0[0x8];
2011 	u8         port_number[0x8];
2012 	u8         reserved_1[0x10];
2013 
2014 	u8         reserved_2[0x1a];
2015 	u8         num_app_prio[0x6];
2016 
2017 	u8         reserved_3[0x40];
2018 
2019 	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
2020 };
2021 
2022 struct mlx5_ifc_dcbx_param_reg_bits {
2023 	u8         dcbx_cee_cap[0x1];
2024 	u8         dcbx_ieee_cap[0x1];
2025 	u8         dcbx_standby_cap[0x1];
2026 	u8         reserved_0[0x5];
2027 	u8         port_number[0x8];
2028 	u8         reserved_1[0xa];
2029 	u8         max_application_table_size[0x6];
2030 
2031 	u8         reserved_2[0x15];
2032 	u8         version_oper[0x3];
2033 	u8         reserved_3[0x5];
2034 	u8         version_admin[0x3];
2035 
2036 	u8         willing_admin[0x1];
2037 	u8         reserved_4[0x3];
2038 	u8         pfc_cap_oper[0x4];
2039 	u8         reserved_5[0x4];
2040 	u8         pfc_cap_admin[0x4];
2041 	u8         reserved_6[0x4];
2042 	u8         num_of_tc_oper[0x4];
2043 	u8         reserved_7[0x4];
2044 	u8         num_of_tc_admin[0x4];
2045 
2046 	u8         remote_willing[0x1];
2047 	u8         reserved_8[0x3];
2048 	u8         remote_pfc_cap[0x4];
2049 	u8         reserved_9[0x14];
2050 	u8         remote_num_of_tc[0x4];
2051 
2052 	u8         reserved_10[0x18];
2053 	u8         error[0x8];
2054 
2055 	u8         reserved_11[0x160];
2056 };
2057 
2058 struct mlx5_ifc_qhll_bits {
2059 	u8         reserved_at_0[0x8];
2060 	u8         local_port[0x8];
2061 	u8         reserved_at_10[0x10];
2062 
2063 	u8         reserved_at_20[0x1b];
2064 	u8         hll_time[0x5];
2065 
2066 	u8         stall_en[0x1];
2067 	u8         reserved_at_41[0x1c];
2068 	u8         stall_cnt[0x3];
2069 };
2070 
2071 struct mlx5_ifc_qetcr_reg_bits {
2072 	u8         operation_type[0x2];
2073 	u8         cap_local_admin[0x1];
2074 	u8         cap_remote_admin[0x1];
2075 	u8         reserved_0[0x4];
2076 	u8         port_number[0x8];
2077 	u8         reserved_1[0x10];
2078 
2079 	u8         reserved_2[0x20];
2080 
2081 	u8         tc[8][0x40];
2082 
2083 	u8         global_configuration[0x40];
2084 };
2085 
2086 struct mlx5_ifc_nodnic_ring_config_reg_bits {
2087 	u8         queue_address_63_32[0x20];
2088 
2089 	u8         queue_address_31_12[0x14];
2090 	u8         reserved_0[0x6];
2091 	u8         log_size[0x6];
2092 
2093 	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
2094 
2095 	u8         reserved_1[0x8];
2096 	u8         queue_number[0x18];
2097 
2098 	u8         q_key[0x20];
2099 
2100 	u8         reserved_2[0x10];
2101 	u8         pkey_index[0x10];
2102 
2103 	u8         reserved_3[0x40];
2104 };
2105 
2106 struct mlx5_ifc_nodnic_cq_arming_word_bits {
2107 	u8         reserved_0[0x8];
2108 	u8         cq_ci[0x10];
2109 	u8         reserved_1[0x8];
2110 };
2111 
2112 enum {
2113 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
2114 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
2115 };
2116 
2117 enum {
2118 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
2119 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
2120 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
2121 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
2122 };
2123 
2124 struct mlx5_ifc_nodnic_event_word_bits {
2125 	u8         driver_reset_needed[0x1];
2126 	u8         port_management_change_event[0x1];
2127 	u8         reserved_0[0x19];
2128 	u8         link_type[0x1];
2129 	u8         port_state[0x4];
2130 };
2131 
2132 struct mlx5_ifc_nic_vport_change_event_bits {
2133 	u8         reserved_0[0x10];
2134 	u8         vport_num[0x10];
2135 
2136 	u8         reserved_1[0xc0];
2137 };
2138 
2139 struct mlx5_ifc_pages_req_event_bits {
2140 	u8         reserved_0[0x10];
2141 	u8         function_id[0x10];
2142 
2143 	u8         num_pages[0x20];
2144 
2145 	u8         reserved_1[0xa0];
2146 };
2147 
2148 struct mlx5_ifc_cmd_inter_comp_event_bits {
2149 	u8         command_completion_vector[0x20];
2150 
2151 	u8         reserved_0[0xc0];
2152 };
2153 
2154 struct mlx5_ifc_stall_vl_event_bits {
2155 	u8         reserved_0[0x18];
2156 	u8         port_num[0x1];
2157 	u8         reserved_1[0x3];
2158 	u8         vl[0x4];
2159 
2160 	u8         reserved_2[0xa0];
2161 };
2162 
2163 struct mlx5_ifc_db_bf_congestion_event_bits {
2164 	u8         event_subtype[0x8];
2165 	u8         reserved_0[0x8];
2166 	u8         congestion_level[0x8];
2167 	u8         reserved_1[0x8];
2168 
2169 	u8         reserved_2[0xa0];
2170 };
2171 
2172 struct mlx5_ifc_gpio_event_bits {
2173 	u8         reserved_0[0x60];
2174 
2175 	u8         gpio_event_hi[0x20];
2176 
2177 	u8         gpio_event_lo[0x20];
2178 
2179 	u8         reserved_1[0x40];
2180 };
2181 
2182 struct mlx5_ifc_port_state_change_event_bits {
2183 	u8         reserved_0[0x40];
2184 
2185 	u8         port_num[0x4];
2186 	u8         reserved_1[0x1c];
2187 
2188 	u8         reserved_2[0x80];
2189 };
2190 
2191 struct mlx5_ifc_dropped_packet_logged_bits {
2192 	u8         reserved_0[0xe0];
2193 };
2194 
2195 enum {
2196 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2197 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2198 };
2199 
2200 struct mlx5_ifc_cq_error_bits {
2201 	u8         reserved_0[0x8];
2202 	u8         cqn[0x18];
2203 
2204 	u8         reserved_1[0x20];
2205 
2206 	u8         reserved_2[0x18];
2207 	u8         syndrome[0x8];
2208 
2209 	u8         reserved_3[0x80];
2210 };
2211 
2212 struct mlx5_ifc_rdma_page_fault_event_bits {
2213 	u8         bytes_commited[0x20];
2214 
2215 	u8         r_key[0x20];
2216 
2217 	u8         reserved_0[0x10];
2218 	u8         packet_len[0x10];
2219 
2220 	u8         rdma_op_len[0x20];
2221 
2222 	u8         rdma_va[0x40];
2223 
2224 	u8         reserved_1[0x5];
2225 	u8         rdma[0x1];
2226 	u8         write[0x1];
2227 	u8         requestor[0x1];
2228 	u8         qp_number[0x18];
2229 };
2230 
2231 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2232 	u8         bytes_committed[0x20];
2233 
2234 	u8         reserved_0[0x10];
2235 	u8         wqe_index[0x10];
2236 
2237 	u8         reserved_1[0x10];
2238 	u8         len[0x10];
2239 
2240 	u8         reserved_2[0x60];
2241 
2242 	u8         reserved_3[0x5];
2243 	u8         rdma[0x1];
2244 	u8         write_read[0x1];
2245 	u8         requestor[0x1];
2246 	u8         qpn[0x18];
2247 };
2248 
2249 enum {
2250 	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
2251 	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
2252 	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
2253 };
2254 
2255 struct mlx5_ifc_qp_events_bits {
2256 	u8         reserved_0[0xa0];
2257 
2258 	u8         type[0x8];
2259 	u8         reserved_1[0x18];
2260 
2261 	u8         reserved_2[0x8];
2262 	u8         qpn_rqn_sqn[0x18];
2263 };
2264 
2265 struct mlx5_ifc_dct_events_bits {
2266 	u8         reserved_0[0xc0];
2267 
2268 	u8         reserved_1[0x8];
2269 	u8         dct_number[0x18];
2270 };
2271 
2272 struct mlx5_ifc_comp_event_bits {
2273 	u8         reserved_0[0xc0];
2274 
2275 	u8         reserved_1[0x8];
2276 	u8         cq_number[0x18];
2277 };
2278 
2279 struct mlx5_ifc_fw_version_bits {
2280 	u8         major[0x10];
2281 	u8         reserved_0[0x10];
2282 
2283 	u8         minor[0x10];
2284 	u8         subminor[0x10];
2285 
2286 	u8         second[0x8];
2287 	u8         minute[0x8];
2288 	u8         hour[0x8];
2289 	u8         reserved_1[0x8];
2290 
2291 	u8         year[0x10];
2292 	u8         month[0x8];
2293 	u8         day[0x8];
2294 };
2295 
2296 enum {
2297 	MLX5_QPC_STATE_RST        = 0x0,
2298 	MLX5_QPC_STATE_INIT       = 0x1,
2299 	MLX5_QPC_STATE_RTR        = 0x2,
2300 	MLX5_QPC_STATE_RTS        = 0x3,
2301 	MLX5_QPC_STATE_SQER       = 0x4,
2302 	MLX5_QPC_STATE_SQD        = 0x5,
2303 	MLX5_QPC_STATE_ERR        = 0x6,
2304 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
2305 };
2306 
2307 enum {
2308 	MLX5_QPC_ST_RC            = 0x0,
2309 	MLX5_QPC_ST_UC            = 0x1,
2310 	MLX5_QPC_ST_UD            = 0x2,
2311 	MLX5_QPC_ST_XRC           = 0x3,
2312 	MLX5_QPC_ST_DCI           = 0x5,
2313 	MLX5_QPC_ST_QP0           = 0x7,
2314 	MLX5_QPC_ST_QP1           = 0x8,
2315 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2316 	MLX5_QPC_ST_REG_UMR       = 0xc,
2317 };
2318 
2319 enum {
2320 	MLX5_QP_PM_ARMED            = 0x0,
2321 	MLX5_QP_PM_REARM            = 0x1,
2322 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2323 	MLX5_QP_PM_MIGRATED         = 0x3,
2324 };
2325 
2326 enum {
2327 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2328 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2329 };
2330 
2331 enum {
2332 	MLX5_QPC_MTU_256_BYTES        = 0x1,
2333 	MLX5_QPC_MTU_512_BYTES        = 0x2,
2334 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2335 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2336 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2337 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2338 };
2339 
2340 enum {
2341 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2342 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2343 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2344 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2345 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2346 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2347 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2348 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2349 };
2350 
2351 enum {
2352 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2353 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2354 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2355 };
2356 
2357 enum {
2358 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2359 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2360 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2361 };
2362 
2363 enum {
2364 	MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2365 	MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2366 	MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2367 };
2368 
2369 struct mlx5_ifc_qpc_bits {
2370 	u8         state[0x4];
2371 	u8         lag_tx_port_affinity[0x4];
2372 	u8         st[0x8];
2373 	u8         reserved_1[0x3];
2374 	u8         pm_state[0x2];
2375 	u8         reserved_2[0x7];
2376 	u8         end_padding_mode[0x2];
2377 	u8         reserved_3[0x2];
2378 
2379 	u8         wq_signature[0x1];
2380 	u8         block_lb_mc[0x1];
2381 	u8         atomic_like_write_en[0x1];
2382 	u8         latency_sensitive[0x1];
2383 	u8         reserved_4[0x1];
2384 	u8         drain_sigerr[0x1];
2385 	u8         reserved_5[0x2];
2386 	u8         pd[0x18];
2387 
2388 	u8         mtu[0x3];
2389 	u8         log_msg_max[0x5];
2390 	u8         reserved_6[0x1];
2391 	u8         log_rq_size[0x4];
2392 	u8         log_rq_stride[0x3];
2393 	u8         no_sq[0x1];
2394 	u8         log_sq_size[0x4];
2395 	u8         reserved_at_55[0x3];
2396 	u8         ts_format[0x2];
2397 	u8         reserved_at_5a[0x1];
2398 	u8         rlky[0x1];
2399 	u8         ulp_stateless_offload_mode[0x4];
2400 
2401 	u8         counter_set_id[0x8];
2402 	u8         uar_page[0x18];
2403 
2404 	u8         reserved_8[0x8];
2405 	u8         user_index[0x18];
2406 
2407 	u8         reserved_9[0x3];
2408 	u8         log_page_size[0x5];
2409 	u8         remote_qpn[0x18];
2410 
2411 	struct mlx5_ifc_ads_bits primary_address_path;
2412 
2413 	struct mlx5_ifc_ads_bits secondary_address_path;
2414 
2415 	u8         log_ack_req_freq[0x4];
2416 	u8         reserved_10[0x4];
2417 	u8         log_sra_max[0x3];
2418 	u8         reserved_11[0x2];
2419 	u8         retry_count[0x3];
2420 	u8         rnr_retry[0x3];
2421 	u8         reserved_12[0x1];
2422 	u8         fre[0x1];
2423 	u8         cur_rnr_retry[0x3];
2424 	u8         cur_retry_count[0x3];
2425 	u8         reserved_13[0x5];
2426 
2427 	u8         reserved_14[0x20];
2428 
2429 	u8         reserved_15[0x8];
2430 	u8         next_send_psn[0x18];
2431 
2432 	u8         reserved_16[0x8];
2433 	u8         cqn_snd[0x18];
2434 
2435 	u8         reserved_at_400[0x8];
2436 
2437 	u8         deth_sqpn[0x18];
2438 	u8         reserved_17[0x20];
2439 
2440 	u8         reserved_18[0x8];
2441 	u8         last_acked_psn[0x18];
2442 
2443 	u8         reserved_19[0x8];
2444 	u8         ssn[0x18];
2445 
2446 	u8         reserved_20[0x8];
2447 	u8         log_rra_max[0x3];
2448 	u8         reserved_21[0x1];
2449 	u8         atomic_mode[0x4];
2450 	u8         rre[0x1];
2451 	u8         rwe[0x1];
2452 	u8         rae[0x1];
2453 	u8         reserved_22[0x1];
2454 	u8         page_offset[0x6];
2455 	u8         reserved_23[0x3];
2456 	u8         cd_slave_receive[0x1];
2457 	u8         cd_slave_send[0x1];
2458 	u8         cd_master[0x1];
2459 
2460 	u8         reserved_24[0x3];
2461 	u8         min_rnr_nak[0x5];
2462 	u8         next_rcv_psn[0x18];
2463 
2464 	u8         reserved_25[0x8];
2465 	u8         xrcd[0x18];
2466 
2467 	u8         reserved_26[0x8];
2468 	u8         cqn_rcv[0x18];
2469 
2470 	u8         dbr_addr[0x40];
2471 
2472 	u8         q_key[0x20];
2473 
2474 	u8         reserved_27[0x5];
2475 	u8         rq_type[0x3];
2476 	u8         srqn_rmpn[0x18];
2477 
2478 	u8         reserved_28[0x8];
2479 	u8         rmsn[0x18];
2480 
2481 	u8         hw_sq_wqebb_counter[0x10];
2482 	u8         sw_sq_wqebb_counter[0x10];
2483 
2484 	u8         hw_rq_counter[0x20];
2485 
2486 	u8         sw_rq_counter[0x20];
2487 
2488 	u8         reserved_29[0x20];
2489 
2490 	u8         reserved_30[0xf];
2491 	u8         cgs[0x1];
2492 	u8         cs_req[0x8];
2493 	u8         cs_res[0x8];
2494 
2495 	u8         dc_access_key[0x40];
2496 
2497 	u8         reserved_at_680[0x3];
2498 	u8         dbr_umem_valid[0x1];
2499 
2500 	u8         reserved_at_684[0xbc];
2501 };
2502 
2503 struct mlx5_ifc_roce_addr_layout_bits {
2504 	u8         source_l3_address[16][0x8];
2505 
2506 	u8         reserved_0[0x3];
2507 	u8         vlan_valid[0x1];
2508 	u8         vlan_id[0xc];
2509 	u8         source_mac_47_32[0x10];
2510 
2511 	u8         source_mac_31_0[0x20];
2512 
2513 	u8         reserved_1[0x14];
2514 	u8         roce_l3_type[0x4];
2515 	u8         roce_version[0x8];
2516 
2517 	u8         reserved_2[0x20];
2518 };
2519 
2520 struct mlx5_ifc_rdbc_bits {
2521 	u8         reserved_0[0x1c];
2522 	u8         type[0x4];
2523 
2524 	u8         reserved_1[0x20];
2525 
2526 	u8         reserved_2[0x8];
2527 	u8         psn[0x18];
2528 
2529 	u8         rkey[0x20];
2530 
2531 	u8         address[0x40];
2532 
2533 	u8         byte_count[0x20];
2534 
2535 	u8         reserved_3[0x20];
2536 
2537 	u8         atomic_resp[32][0x8];
2538 };
2539 
2540 struct mlx5_ifc_vlan_bits {
2541 	u8         ethtype[0x10];
2542 	u8         prio[0x3];
2543 	u8         cfi[0x1];
2544 	u8         vid[0xc];
2545 };
2546 
2547 enum {
2548 	MLX5_FLOW_METER_COLOR_RED       = 0x0,
2549 	MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
2550 	MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
2551 	MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
2552 };
2553 
2554 enum {
2555 	MLX5_EXE_ASO_FLOW_METER         = 0x2,
2556 };
2557 
2558 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
2559 	u8        return_reg_id[0x4];
2560 	u8        aso_type[0x4];
2561 	u8        reserved_at_8[0x14];
2562 	u8        action[0x1];
2563 	u8        init_color[0x2];
2564 	u8        meter_id[0x1];
2565 };
2566 
2567 union mlx5_ifc_exe_aso_ctrl {
2568 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
2569 };
2570 
2571 struct mlx5_ifc_execute_aso_bits {
2572 	u8        valid[0x1];
2573 	u8        reserved_at_1[0x7];
2574 	u8        aso_object_id[0x18];
2575 
2576 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
2577 };
2578 
2579 enum {
2580 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
2581 };
2582 
2583 struct mlx5_ifc_flow_context_bits {
2584 	struct mlx5_ifc_vlan_bits push_vlan;
2585 
2586 	u8         group_id[0x20];
2587 
2588 	u8         reserved_at_40[0x8];
2589 	u8         flow_tag[0x18];
2590 
2591 	u8         reserved_at_60[0x10];
2592 	u8         action[0x10];
2593 
2594 	u8         extended_destination[0x1];
2595 	u8         reserved_at_81[0x1];
2596 	u8         flow_source[0x2];
2597 	u8         encrypt_decrypt_type[0x4];
2598 	u8         destination_list_size[0x18];
2599 
2600 	u8         reserved_at_a0[0x8];
2601 	u8         flow_counter_list_size[0x18];
2602 
2603 	u8         packet_reformat_id[0x20];
2604 
2605 	u8         modify_header_id[0x20];
2606 
2607 	struct mlx5_ifc_vlan_bits push_vlan_2;
2608 
2609 	u8         encrypt_decrypt_obj_id[0x20];
2610 	u8         reserved_at_140[0xc0];
2611 
2612 	struct mlx5_ifc_fte_match_param_bits match_value;
2613 
2614 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
2615 
2616 	u8         reserved_at_1300[0x500];
2617 
2618 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
2619 };
2620 
2621 enum {
2622 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2623 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2624 };
2625 
2626 struct mlx5_ifc_xrc_srqc_bits {
2627 	u8         state[0x4];
2628 	u8         log_xrc_srq_size[0x4];
2629 	u8         reserved_0[0x18];
2630 
2631 	u8         wq_signature[0x1];
2632 	u8         cont_srq[0x1];
2633 	u8         reserved_1[0x1];
2634 	u8         rlky[0x1];
2635 	u8         basic_cyclic_rcv_wqe[0x1];
2636 	u8         log_rq_stride[0x3];
2637 	u8         xrcd[0x18];
2638 
2639 	u8         page_offset[0x6];
2640 	u8         reserved_at_46[0x1];
2641 	u8         dbr_umem_valid[0x1];
2642 	u8         cqn[0x18];
2643 
2644 	u8         reserved_3[0x20];
2645 
2646 	u8         reserved_4[0x2];
2647 	u8         log_page_size[0x6];
2648 	u8         user_index[0x18];
2649 
2650 	u8         reserved_5[0x20];
2651 
2652 	u8         reserved_6[0x8];
2653 	u8         pd[0x18];
2654 
2655 	u8         lwm[0x10];
2656 	u8         wqe_cnt[0x10];
2657 
2658 	u8         reserved_7[0x40];
2659 
2660 	u8         db_record_addr_h[0x20];
2661 
2662 	u8         db_record_addr_l[0x1e];
2663 	u8         reserved_8[0x2];
2664 
2665 	u8         reserved_9[0x80];
2666 };
2667 
2668 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2669 	u8         counter_error_queues[0x20];
2670 
2671 	u8         total_error_queues[0x20];
2672 
2673 	u8         send_queue_priority_update_flow[0x20];
2674 
2675 	u8         reserved_at_60[0x20];
2676 
2677 	u8         nic_receive_steering_discard[0x40];
2678 
2679 	u8         receive_discard_vport_down[0x40];
2680 
2681 	u8         transmit_discard_vport_down[0x40];
2682 
2683 	u8         reserved_at_140[0xec0];
2684 };
2685 
2686 struct mlx5_ifc_traffic_counter_bits {
2687 	u8         packets[0x40];
2688 
2689 	u8         octets[0x40];
2690 };
2691 
2692 struct mlx5_ifc_tisc_bits {
2693 	u8         strict_lag_tx_port_affinity[0x1];
2694 	u8         tls_en[0x1];
2695 	u8         reserved_at_2[0x2];
2696 	u8         lag_tx_port_affinity[0x04];
2697 
2698 	u8         reserved_at_8[0x4];
2699 	u8         prio[0x4];
2700 	u8         reserved_1[0x10];
2701 
2702 	u8         reserved_2[0x100];
2703 
2704 	u8         reserved_3[0x8];
2705 	u8         transport_domain[0x18];
2706 
2707 	u8         reserved_4[0x8];
2708 	u8         underlay_qpn[0x18];
2709 
2710 	u8         reserved_5[0x8];
2711 	u8         pd[0x18];
2712 
2713 	u8         reserved_6[0x380];
2714 };
2715 
2716 enum {
2717 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2718 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2719 };
2720 
2721 enum {
2722 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2723 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2724 };
2725 
2726 enum {
2727 	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2728 	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2729 	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2730 };
2731 
2732 enum {
2733 	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2734 	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2735 };
2736 
2737 struct mlx5_ifc_tirc_bits {
2738 	u8         reserved_0[0x20];
2739 
2740 	u8         disp_type[0x4];
2741 	u8         tls_en[0x1];
2742 	u8         reserved_at_25[0x1b];
2743 
2744 	u8         reserved_2[0x40];
2745 
2746 	u8         reserved_3[0x4];
2747 	u8         lro_timeout_period_usecs[0x10];
2748 	u8         lro_enable_mask[0x4];
2749 	u8         lro_max_msg_sz[0x8];
2750 
2751 	u8         reserved_4[0x40];
2752 
2753 	u8         reserved_5[0x8];
2754 	u8         inline_rqn[0x18];
2755 
2756 	u8         rx_hash_symmetric[0x1];
2757 	u8         reserved_6[0x1];
2758 	u8         tunneled_offload_en[0x1];
2759 	u8         reserved_7[0x5];
2760 	u8         indirect_table[0x18];
2761 
2762 	u8         rx_hash_fn[0x4];
2763 	u8         reserved_8[0x2];
2764 	u8         self_lb_en[0x2];
2765 	u8         transport_domain[0x18];
2766 
2767 	u8         rx_hash_toeplitz_key[10][0x20];
2768 
2769 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2770 
2771 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2772 
2773 	u8         reserved_9[0x4c0];
2774 };
2775 
2776 enum {
2777 	MLX5_SRQC_STATE_GOOD   = 0x0,
2778 	MLX5_SRQC_STATE_ERROR  = 0x1,
2779 };
2780 
2781 struct mlx5_ifc_srqc_bits {
2782 	u8         state[0x4];
2783 	u8         log_srq_size[0x4];
2784 	u8         reserved_0[0x18];
2785 
2786 	u8         wq_signature[0x1];
2787 	u8         cont_srq[0x1];
2788 	u8         reserved_1[0x1];
2789 	u8         rlky[0x1];
2790 	u8         reserved_2[0x1];
2791 	u8         log_rq_stride[0x3];
2792 	u8         xrcd[0x18];
2793 
2794 	u8         page_offset[0x6];
2795 	u8         reserved_3[0x2];
2796 	u8         cqn[0x18];
2797 
2798 	u8         reserved_4[0x20];
2799 
2800 	u8         reserved_5[0x2];
2801 	u8         log_page_size[0x6];
2802 	u8         reserved_6[0x18];
2803 
2804 	u8         reserved_7[0x20];
2805 
2806 	u8         reserved_8[0x8];
2807 	u8         pd[0x18];
2808 
2809 	u8         lwm[0x10];
2810 	u8         wqe_cnt[0x10];
2811 
2812 	u8         reserved_9[0x40];
2813 
2814 	u8	   dbr_addr[0x40];
2815 
2816 	u8	   reserved_10[0x80];
2817 };
2818 
2819 enum {
2820 	MLX5_SQC_STATE_RST  = 0x0,
2821 	MLX5_SQC_STATE_RDY  = 0x1,
2822 	MLX5_SQC_STATE_ERR  = 0x3,
2823 };
2824 
2825 enum {
2826 	MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2827 	MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2828 	MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2829 };
2830 
2831 struct mlx5_ifc_sqc_bits {
2832 	u8         rlkey[0x1];
2833 	u8         cd_master[0x1];
2834 	u8         fre[0x1];
2835 	u8         flush_in_error_en[0x1];
2836 	u8         allow_multi_pkt_send_wqe[0x1];
2837 	u8         min_wqe_inline_mode[0x3];
2838 	u8         state[0x4];
2839 	u8         reg_umr[0x1];
2840 	u8         allow_swp[0x1];
2841 	u8         reserved_at_e[0x4];
2842 	u8	   qos_remap_en[0x1];
2843 	u8	   reserved_at_d[0x7];
2844 	u8         ts_format[0x2];
2845 	u8         reserved_at_1c[0x4];
2846 
2847 	u8         reserved_1[0x8];
2848 	u8         user_index[0x18];
2849 
2850 	u8         reserved_2[0x8];
2851 	u8         cqn[0x18];
2852 
2853 	u8         reserved_3[0x80];
2854 
2855 	u8         qos_para_vport_number[0x10];
2856 	u8         packet_pacing_rate_limit_index[0x10];
2857 
2858 	u8         tis_lst_sz[0x10];
2859 	u8         qos_queue_group_id[0x10];
2860 
2861 	u8	   reserved_4[0x8];
2862 	u8	   queue_handle[0x18];
2863 
2864 	u8         reserved_5[0x20];
2865 
2866 	u8         reserved_6[0x8];
2867 	u8         tis_num_0[0x18];
2868 
2869 	struct mlx5_ifc_wq_bits wq;
2870 };
2871 
2872 struct mlx5_ifc_query_pp_rate_limit_in_bits {
2873 	u8	   opcode[0x10];
2874 	u8	   uid[0x10];
2875 
2876 	u8	   reserved1[0x10];
2877 	u8         op_mod[0x10];
2878 
2879 	u8         reserved2[0x10];
2880         u8         rate_limit_index[0x10];
2881 
2882 	u8         reserved_3[0x20];
2883 };
2884 
2885 struct mlx5_ifc_pp_context_bits {
2886 	u8	   rate_limit[0x20];
2887 
2888 	u8	   burst_upper_bound[0x20];
2889 
2890 	u8	   reserved_1[0xc];
2891 	u8	   rate_mode[0x4];
2892 	u8	   typical_packet_size[0x10];
2893 
2894 	u8	   reserved_2[0x8];
2895 	u8	   qos_handle[0x18];
2896 
2897 	u8	   reserved_3[0x40];
2898 };
2899 
2900 struct mlx5_ifc_query_pp_rate_limit_out_bits {
2901         u8	   status[0x8];
2902 	u8         reserved_1[0x18];
2903 
2904         u8         syndrome[0x20];
2905 
2906         u8         reserved_2[0x40];
2907 
2908 	struct mlx5_ifc_pp_context_bits pp_context;
2909 };
2910 
2911 enum {
2912 	MLX5_TSAR_TYPE_DWRR = 0,
2913 	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2914 	MLX5_TSAR_TYPE_ETS = 2
2915 };
2916 
2917 struct mlx5_ifc_tsar_element_attributes_bits {
2918 	u8         reserved_0[0x8];
2919 	u8         tsar_type[0x8];
2920 	u8	   reserved_1[0x10];
2921 };
2922 
2923 struct mlx5_ifc_vport_element_attributes_bits {
2924 	u8         reserved_0[0x10];
2925 	u8         vport_number[0x10];
2926 };
2927 
2928 struct mlx5_ifc_vport_tc_element_attributes_bits {
2929 	u8         traffic_class[0x10];
2930 	u8         vport_number[0x10];
2931 };
2932 
2933 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2934 	u8         reserved_0[0x0C];
2935 	u8         traffic_class[0x04];
2936 	u8         qos_para_vport_number[0x10];
2937 };
2938 
2939 enum {
2940 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2941 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2942 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2943 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2944 };
2945 
2946 struct mlx5_ifc_scheduling_context_bits {
2947 	u8         element_type[0x8];
2948 	u8         reserved_at_8[0x18];
2949 
2950 	u8         element_attributes[0x20];
2951 
2952 	u8         parent_element_id[0x20];
2953 
2954 	u8         reserved_at_60[0x40];
2955 
2956 	u8         bw_share[0x20];
2957 
2958 	u8         max_average_bw[0x20];
2959 
2960 	u8         reserved_at_e0[0x120];
2961 };
2962 
2963 struct mlx5_ifc_rqtc_bits {
2964 	u8         reserved_0[0xa0];
2965 
2966 	u8         reserved_1[0x10];
2967 	u8         rqt_max_size[0x10];
2968 
2969 	u8         reserved_2[0x10];
2970 	u8         rqt_actual_size[0x10];
2971 
2972 	u8         reserved_3[0x6a0];
2973 
2974 	struct mlx5_ifc_rq_num_bits rq_num[0];
2975 };
2976 
2977 enum {
2978 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2979 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2980 };
2981 
2982 enum {
2983 	MLX5_RQC_STATE_RST  = 0x0,
2984 	MLX5_RQC_STATE_RDY  = 0x1,
2985 	MLX5_RQC_STATE_ERR  = 0x3,
2986 };
2987 
2988 enum {
2989 	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2990 	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2991 };
2992 
2993 enum {
2994 	MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2995 	MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2996 	MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2997 };
2998 
2999 struct mlx5_ifc_rqc_bits {
3000 	u8         rlkey[0x1];
3001 	u8         delay_drop_en[0x1];
3002 	u8         scatter_fcs[0x1];
3003 	u8         vlan_strip_disable[0x1];
3004 	u8         mem_rq_type[0x4];
3005 	u8         state[0x4];
3006 	u8         reserved_1[0x1];
3007 	u8         flush_in_error_en[0x1];
3008 	u8         reserved_at_e[0xc];
3009 	u8         ts_format[0x2];
3010 	u8         reserved_at_1c[0x4];
3011 
3012 	u8         reserved_3[0x8];
3013 	u8         user_index[0x18];
3014 
3015 	u8         reserved_4[0x8];
3016 	u8         cqn[0x18];
3017 
3018 	u8         counter_set_id[0x8];
3019 	u8         reserved_5[0x18];
3020 
3021 	u8         reserved_6[0x8];
3022 	u8         rmpn[0x18];
3023 
3024 	u8         reserved_7[0xe0];
3025 
3026 	struct mlx5_ifc_wq_bits wq;
3027 };
3028 
3029 enum {
3030 	MLX5_RMPC_STATE_RDY  = 0x1,
3031 	MLX5_RMPC_STATE_ERR  = 0x3,
3032 };
3033 
3034 struct mlx5_ifc_rmpc_bits {
3035 	u8         reserved_0[0x8];
3036 	u8         state[0x4];
3037 	u8         reserved_1[0x14];
3038 
3039 	u8         basic_cyclic_rcv_wqe[0x1];
3040 	u8         reserved_2[0x1f];
3041 
3042 	u8         reserved_3[0x140];
3043 
3044 	struct mlx5_ifc_wq_bits wq;
3045 };
3046 
3047 enum {
3048 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
3049 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
3050 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
3051 };
3052 
3053 struct mlx5_ifc_nic_vport_context_bits {
3054 	u8         reserved_0[0x5];
3055 	u8         min_wqe_inline_mode[0x3];
3056 	u8         reserved_1[0x15];
3057 	u8         disable_mc_local_lb[0x1];
3058 	u8         disable_uc_local_lb[0x1];
3059 	u8         roce_en[0x1];
3060 
3061 	u8         arm_change_event[0x1];
3062 	u8         reserved_2[0x1a];
3063 	u8         event_on_mtu[0x1];
3064 	u8         event_on_promisc_change[0x1];
3065 	u8         event_on_vlan_change[0x1];
3066 	u8         event_on_mc_address_change[0x1];
3067 	u8         event_on_uc_address_change[0x1];
3068 
3069 	u8         reserved_3[0xe0];
3070 
3071 	u8         reserved_4[0x10];
3072 	u8         mtu[0x10];
3073 
3074 	u8         system_image_guid[0x40];
3075 
3076 	u8         port_guid[0x40];
3077 
3078 	u8         node_guid[0x40];
3079 
3080 	u8         reserved_5[0x140];
3081 
3082 	u8         qkey_violation_counter[0x10];
3083 	u8         reserved_6[0x10];
3084 
3085 	u8         reserved_7[0x420];
3086 
3087 	u8         promisc_uc[0x1];
3088 	u8         promisc_mc[0x1];
3089 	u8         promisc_all[0x1];
3090 	u8         reserved_8[0x2];
3091 	u8         allowed_list_type[0x3];
3092 	u8         reserved_9[0xc];
3093 	u8         allowed_list_size[0xc];
3094 
3095 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
3096 
3097 	u8         reserved_10[0x20];
3098 
3099 	u8         current_uc_mac_address[0][0x40];
3100 };
3101 
3102 enum {
3103 	MLX5_ACCESS_MODE_PA        = 0x0,
3104 	MLX5_ACCESS_MODE_MTT       = 0x1,
3105 	MLX5_ACCESS_MODE_KLM       = 0x2,
3106 	MLX5_ACCESS_MODE_KSM       = 0x3,
3107 	MLX5_ACCESS_MODE_SW_ICM    = 0x4,
3108 	MLX5_ACCESS_MODE_MEMIC     = 0x5,
3109 };
3110 
3111 struct mlx5_ifc_mkc_bits {
3112 	u8         reserved_at_0[0x1];
3113 	u8         free[0x1];
3114 	u8         reserved_at_2[0x1];
3115 	u8         access_mode_4_2[0x3];
3116 	u8         reserved_at_6[0x7];
3117 	u8         relaxed_ordering_write[0x1];
3118 	u8         reserved_at_e[0x1];
3119 	u8         small_fence_on_rdma_read_response[0x1];
3120 	u8         umr_en[0x1];
3121 	u8         a[0x1];
3122 	u8         rw[0x1];
3123 	u8         rr[0x1];
3124 	u8         lw[0x1];
3125 	u8         lr[0x1];
3126 	u8         access_mode[0x2];
3127 	u8         reserved_2[0x8];
3128 
3129 	u8         qpn[0x18];
3130 	u8         mkey_7_0[0x8];
3131 
3132 	u8         reserved_3[0x20];
3133 
3134 	u8         length64[0x1];
3135 	u8         bsf_en[0x1];
3136 	u8         sync_umr[0x1];
3137 	u8         reserved_4[0x2];
3138 	u8         expected_sigerr_count[0x1];
3139 	u8         reserved_5[0x1];
3140 	u8         en_rinval[0x1];
3141 	u8         pd[0x18];
3142 
3143 	u8         start_addr[0x40];
3144 
3145 	u8         len[0x40];
3146 
3147 	u8         bsf_octword_size[0x20];
3148 
3149 	u8         reserved_6[0x80];
3150 
3151 	u8         translations_octword_size[0x20];
3152 
3153 	u8         reserved_at_1c0[0x19];
3154 	u8         relaxed_ordering_read[0x1];
3155 	u8         reserved_at_1d9[0x1];
3156 	u8         log_page_size[0x5];
3157 
3158 	u8         reserved_8[0x20];
3159 };
3160 
3161 struct mlx5_ifc_pkey_bits {
3162 	u8         reserved_0[0x10];
3163 	u8         pkey[0x10];
3164 };
3165 
3166 struct mlx5_ifc_array128_auto_bits {
3167 	u8         array128_auto[16][0x8];
3168 };
3169 
3170 enum {
3171 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
3172 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
3173 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
3174 };
3175 
3176 enum {
3177 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
3178 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
3179 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
3180 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
3181 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
3182 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
3183 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
3184 };
3185 
3186 enum {
3187 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
3188 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
3189 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
3190 };
3191 
3192 enum {
3193 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
3194 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
3195 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
3196 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
3197 };
3198 
3199 enum {
3200 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
3201 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
3202 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
3203 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
3204 };
3205 
3206 struct mlx5_ifc_hca_vport_context_bits {
3207 	u8         field_select[0x20];
3208 
3209 	u8         reserved_0[0xe0];
3210 
3211 	u8         sm_virt_aware[0x1];
3212 	u8         has_smi[0x1];
3213 	u8         has_raw[0x1];
3214 	u8         grh_required[0x1];
3215 	u8         reserved_1[0x1];
3216 	u8         min_wqe_inline_mode[0x3];
3217 	u8         reserved_2[0x8];
3218 	u8         port_physical_state[0x4];
3219 	u8         vport_state_policy[0x4];
3220 	u8         port_state[0x4];
3221 	u8         vport_state[0x4];
3222 
3223 	u8         reserved_3[0x20];
3224 
3225 	u8         system_image_guid[0x40];
3226 
3227 	u8         port_guid[0x40];
3228 
3229 	u8         node_guid[0x40];
3230 
3231 	u8         cap_mask1[0x20];
3232 
3233 	u8         cap_mask1_field_select[0x20];
3234 
3235 	u8         cap_mask2[0x20];
3236 
3237 	u8         cap_mask2_field_select[0x20];
3238 
3239 	u8         reserved_4[0x80];
3240 
3241 	u8         lid[0x10];
3242 	u8         reserved_5[0x4];
3243 	u8         init_type_reply[0x4];
3244 	u8         lmc[0x3];
3245 	u8         subnet_timeout[0x5];
3246 
3247 	u8         sm_lid[0x10];
3248 	u8         sm_sl[0x4];
3249 	u8         reserved_6[0xc];
3250 
3251 	u8         qkey_violation_counter[0x10];
3252 	u8         pkey_violation_counter[0x10];
3253 
3254 	u8         reserved_7[0xca0];
3255 };
3256 
3257 union mlx5_ifc_hca_cap_union_bits {
3258 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3259 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3260 	struct mlx5_ifc_odp_cap_bits odp_cap;
3261 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3262 	struct mlx5_ifc_roce_cap_bits roce_cap;
3263 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3264 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3265 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3266 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3267 	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
3268 	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
3269 	struct mlx5_ifc_qos_cap_bits qos_cap;
3270 	struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
3271 	u8         reserved_0[0x8000];
3272 };
3273 
3274 enum {
3275 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
3276 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
3277 };
3278 
3279 struct mlx5_ifc_flow_table_context_bits {
3280         u8         reformat_en[0x1];
3281         u8         decap_en[0x1];
3282         u8         sw_owner[0x1];
3283         u8         termination_table[0x1];
3284         u8         table_miss_action[0x4];
3285         u8         level[0x8];
3286         u8         reserved_at_10[0x8];
3287         u8         log_size[0x8];
3288 
3289         u8         reserved_at_20[0x8];
3290         u8         table_miss_id[0x18];
3291 
3292         u8         reserved_at_40[0x8];
3293         u8         lag_master_next_table_id[0x18];
3294 
3295         u8         reserved_at_60[0x60];
3296 
3297         u8         sw_owner_icm_root_1[0x40];
3298 
3299         u8         sw_owner_icm_root_0[0x40];
3300 
3301 };
3302 
3303 struct mlx5_ifc_esw_vport_context_bits {
3304 	u8         reserved_0[0x3];
3305 	u8         vport_svlan_strip[0x1];
3306 	u8         vport_cvlan_strip[0x1];
3307 	u8         vport_svlan_insert[0x1];
3308 	u8         vport_cvlan_insert[0x2];
3309 	u8         reserved_1[0x18];
3310 
3311 	u8         reserved_2[0x20];
3312 
3313 	u8         svlan_cfi[0x1];
3314 	u8         svlan_pcp[0x3];
3315 	u8         svlan_id[0xc];
3316 	u8         cvlan_cfi[0x1];
3317 	u8         cvlan_pcp[0x3];
3318 	u8         cvlan_id[0xc];
3319 
3320 	u8         reserved_3[0x7a0];
3321 };
3322 
3323 enum {
3324 	MLX5_EQC_STATUS_OK                = 0x0,
3325 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3326 };
3327 
3328 enum {
3329 	MLX5_EQ_STATE_ARMED = 0x9,
3330 	MLX5_EQ_STATE_FIRED = 0xa,
3331 };
3332 
3333 struct mlx5_ifc_eqc_bits {
3334 	u8         status[0x4];
3335 	u8         reserved_0[0x9];
3336 	u8         ec[0x1];
3337 	u8         oi[0x1];
3338 	u8         reserved_1[0x5];
3339 	u8         st[0x4];
3340 	u8         reserved_2[0x8];
3341 
3342 	u8         reserved_3[0x20];
3343 
3344 	u8         reserved_4[0x14];
3345 	u8         page_offset[0x6];
3346 	u8         reserved_5[0x6];
3347 
3348 	u8         reserved_6[0x3];
3349 	u8         log_eq_size[0x5];
3350 	u8         uar_page[0x18];
3351 
3352 	u8         reserved_7[0x20];
3353 
3354 	u8         reserved_8[0x18];
3355 	u8         intr[0x8];
3356 
3357 	u8         reserved_9[0x3];
3358 	u8         log_page_size[0x5];
3359 	u8         reserved_10[0x18];
3360 
3361 	u8         reserved_11[0x60];
3362 
3363 	u8         reserved_12[0x8];
3364 	u8         consumer_counter[0x18];
3365 
3366 	u8         reserved_13[0x8];
3367 	u8         producer_counter[0x18];
3368 
3369 	u8         reserved_14[0x80];
3370 };
3371 
3372 enum {
3373 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
3374 	MLX5_DCTC_STATE_DRAINING  = 0x1,
3375 	MLX5_DCTC_STATE_DRAINED   = 0x2,
3376 };
3377 
3378 enum {
3379 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3380 	MLX5_DCTC_CS_RES_NA         = 0x1,
3381 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3382 };
3383 
3384 enum {
3385 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
3386 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
3387 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3388 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3389 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3390 };
3391 
3392 struct mlx5_ifc_dctc_bits {
3393 	u8         reserved_0[0x4];
3394 	u8         state[0x4];
3395 	u8         reserved_1[0x18];
3396 
3397 	u8         reserved_2[0x8];
3398 	u8         user_index[0x18];
3399 
3400 	u8         reserved_3[0x8];
3401 	u8         cqn[0x18];
3402 
3403 	u8         counter_set_id[0x8];
3404 	u8         atomic_mode[0x4];
3405 	u8         rre[0x1];
3406 	u8         rwe[0x1];
3407 	u8         rae[0x1];
3408 	u8         atomic_like_write_en[0x1];
3409 	u8         latency_sensitive[0x1];
3410 	u8         rlky[0x1];
3411 	u8         reserved_4[0xe];
3412 
3413 	u8         reserved_5[0x8];
3414 	u8         cs_res[0x8];
3415 	u8         reserved_6[0x3];
3416 	u8         min_rnr_nak[0x5];
3417 	u8         reserved_7[0x8];
3418 
3419 	u8         reserved_8[0x8];
3420 	u8         srqn[0x18];
3421 
3422 	u8         reserved_9[0x8];
3423 	u8         pd[0x18];
3424 
3425 	u8         tclass[0x8];
3426 	u8         reserved_10[0x4];
3427 	u8         flow_label[0x14];
3428 
3429 	u8         dc_access_key[0x40];
3430 
3431 	u8         reserved_11[0x5];
3432 	u8         mtu[0x3];
3433 	u8         port[0x8];
3434 	u8         pkey_index[0x10];
3435 
3436 	u8         reserved_12[0x8];
3437 	u8         my_addr_index[0x8];
3438 	u8         reserved_13[0x8];
3439 	u8         hop_limit[0x8];
3440 
3441 	u8         dc_access_key_violation_count[0x20];
3442 
3443 	u8         reserved_14[0x14];
3444 	u8         dei_cfi[0x1];
3445 	u8         eth_prio[0x3];
3446 	u8         ecn[0x2];
3447 	u8         dscp[0x6];
3448 
3449 	u8         reserved_15[0x40];
3450 };
3451 
3452 enum {
3453 	MLX5_CQC_STATUS_OK             = 0x0,
3454 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3455 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3456 };
3457 
3458 enum {
3459 	CQE_SIZE_64                = 0x0,
3460 	CQE_SIZE_128               = 0x1,
3461 };
3462 
3463 enum {
3464 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
3465 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
3466 };
3467 
3468 enum {
3469 	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
3470 	MLX5_CQ_STATE_ARMED                               = 0x9,
3471 	MLX5_CQ_STATE_FIRED                               = 0xa,
3472 };
3473 
3474 struct mlx5_ifc_cqc_bits {
3475 	u8         status[0x4];
3476 	u8         reserved_at_4[0x2];
3477 	u8         dbr_umem_valid[0x1];
3478 	u8         reserved_at_7[0x1];
3479 	u8         cqe_sz[0x3];
3480 	u8         cc[0x1];
3481 	u8         reserved_1[0x1];
3482 	u8         scqe_break_moderation_en[0x1];
3483 	u8         oi[0x1];
3484 	u8         cq_period_mode[0x2];
3485 	u8         cqe_compression_en[0x1];
3486 	u8         mini_cqe_res_format[0x2];
3487 	u8         st[0x4];
3488 	u8         reserved_2[0x8];
3489 
3490 	u8         reserved_3[0x20];
3491 
3492 	u8         reserved_4[0x14];
3493 	u8         page_offset[0x6];
3494 	u8         reserved_5[0x6];
3495 
3496 	u8         reserved_6[0x3];
3497 	u8         log_cq_size[0x5];
3498 	u8         uar_page[0x18];
3499 
3500 	u8         reserved_7[0x4];
3501 	u8         cq_period[0xc];
3502 	u8         cq_max_count[0x10];
3503 
3504 	u8         reserved_8[0x18];
3505 	u8         c_eqn[0x8];
3506 
3507 	u8         reserved_9[0x3];
3508 	u8         log_page_size[0x5];
3509 	u8         reserved_10[0x18];
3510 
3511 	u8         reserved_11[0x20];
3512 
3513 	u8         reserved_12[0x8];
3514 	u8         last_notified_index[0x18];
3515 
3516 	u8         reserved_13[0x8];
3517 	u8         last_solicit_index[0x18];
3518 
3519 	u8         reserved_14[0x8];
3520 	u8         consumer_counter[0x18];
3521 
3522 	u8         reserved_15[0x8];
3523 	u8         producer_counter[0x18];
3524 
3525 	u8         reserved_16[0x40];
3526 
3527 	u8         dbr_addr[0x40];
3528 };
3529 
3530 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3531 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3532 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3533 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3534 	u8         reserved_0[0x800];
3535 };
3536 
3537 struct mlx5_ifc_query_adapter_param_block_bits {
3538 	u8         reserved_0[0xc0];
3539 
3540 	u8         reserved_1[0x8];
3541 	u8         ieee_vendor_id[0x18];
3542 
3543 	u8         reserved_2[0x10];
3544 	u8         vsd_vendor_id[0x10];
3545 
3546 	u8         vsd[208][0x8];
3547 
3548 	u8         vsd_contd_psid[16][0x8];
3549 };
3550 
3551 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3552 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
3553 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3554 	u8         reserved_0[0x20];
3555 };
3556 
3557 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3558 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3559 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3560 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3561 	u8         reserved_0[0x20];
3562 };
3563 
3564 struct mlx5_ifc_bufferx_reg_bits {
3565 	u8         reserved_0[0x6];
3566 	u8         lossy[0x1];
3567 	u8         epsb[0x1];
3568 	u8         reserved_1[0xc];
3569 	u8         size[0xc];
3570 
3571 	u8         xoff_threshold[0x10];
3572 	u8         xon_threshold[0x10];
3573 };
3574 
3575 struct mlx5_ifc_config_item_bits {
3576 	u8         valid[0x2];
3577 	u8         reserved_0[0x2];
3578 	u8         header_type[0x2];
3579 	u8         reserved_1[0x2];
3580 	u8         default_location[0x1];
3581 	u8         reserved_2[0x7];
3582 	u8         version[0x4];
3583 	u8         reserved_3[0x3];
3584 	u8         length[0x9];
3585 
3586 	u8         type[0x20];
3587 
3588 	u8         reserved_4[0x10];
3589 	u8         crc16[0x10];
3590 };
3591 
3592 enum {
3593 	MLX5_XRQC_STATE_GOOD   = 0x0,
3594 	MLX5_XRQC_STATE_ERROR  = 0x1,
3595 };
3596 
3597 enum {
3598 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3599 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3600 };
3601 
3602 enum {
3603 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3604 };
3605 
3606 struct mlx5_ifc_tag_matching_topology_context_bits {
3607 	u8         log_matching_list_sz[0x4];
3608 	u8         reserved_at_4[0xc];
3609 	u8         append_next_index[0x10];
3610 
3611 	u8         sw_phase_cnt[0x10];
3612 	u8         hw_phase_cnt[0x10];
3613 
3614 	u8         reserved_at_40[0x40];
3615 };
3616 
3617 struct mlx5_ifc_xrqc_bits {
3618 	u8         state[0x4];
3619 	u8         rlkey[0x1];
3620 	u8         reserved_at_5[0xf];
3621 	u8         topology[0x4];
3622 	u8         reserved_at_18[0x4];
3623 	u8         offload[0x4];
3624 
3625 	u8         reserved_at_20[0x8];
3626 	u8         user_index[0x18];
3627 
3628 	u8         reserved_at_40[0x8];
3629 	u8         cqn[0x18];
3630 
3631 	u8         reserved_at_60[0xa0];
3632 
3633 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3634 
3635 	u8         reserved_at_180[0x280];
3636 
3637 	struct mlx5_ifc_wq_bits wq;
3638 };
3639 
3640 struct mlx5_ifc_nodnic_port_config_reg_bits {
3641 	struct mlx5_ifc_nodnic_event_word_bits event;
3642 
3643 	u8         network_en[0x1];
3644 	u8         dma_en[0x1];
3645 	u8         promisc_en[0x1];
3646 	u8         promisc_multicast_en[0x1];
3647 	u8         reserved_0[0x17];
3648 	u8         receive_filter_en[0x5];
3649 
3650 	u8         reserved_1[0x10];
3651 	u8         mac_47_32[0x10];
3652 
3653 	u8         mac_31_0[0x20];
3654 
3655 	u8         receive_filters_mgid_mac[64][0x8];
3656 
3657 	u8         gid[16][0x8];
3658 
3659 	u8         reserved_2[0x10];
3660 	u8         lid[0x10];
3661 
3662 	u8         reserved_3[0xc];
3663 	u8         sm_sl[0x4];
3664 	u8         sm_lid[0x10];
3665 
3666 	u8         completion_address_63_32[0x20];
3667 
3668 	u8         completion_address_31_12[0x14];
3669 	u8         reserved_4[0x6];
3670 	u8         log_cq_size[0x6];
3671 
3672 	u8         working_buffer_address_63_32[0x20];
3673 
3674 	u8         working_buffer_address_31_12[0x14];
3675 	u8         reserved_5[0xc];
3676 
3677 	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3678 
3679 	u8         pkey_index[0x10];
3680 	u8         pkey[0x10];
3681 
3682 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3683 
3684 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3685 
3686 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3687 
3688 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3689 
3690 	u8         reserved_6[0x400];
3691 };
3692 
3693 union mlx5_ifc_event_auto_bits {
3694 	struct mlx5_ifc_comp_event_bits comp_event;
3695 	struct mlx5_ifc_dct_events_bits dct_events;
3696 	struct mlx5_ifc_qp_events_bits qp_events;
3697 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3698 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3699 	struct mlx5_ifc_cq_error_bits cq_error;
3700 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3701 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3702 	struct mlx5_ifc_gpio_event_bits gpio_event;
3703 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3704 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3705 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3706 	struct mlx5_ifc_pages_req_event_bits pages_req_event;
3707 	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3708 	u8         reserved_0[0xe0];
3709 };
3710 
3711 struct mlx5_ifc_health_buffer_bits {
3712 	u8         reserved_0[0x100];
3713 
3714 	u8         assert_existptr[0x20];
3715 
3716 	u8         assert_callra[0x20];
3717 
3718 	u8         reserved_1[0x40];
3719 
3720 	u8         fw_version[0x20];
3721 
3722 	u8         hw_id[0x20];
3723 
3724 	u8         reserved_2[0x20];
3725 
3726 	u8         irisc_index[0x8];
3727 	u8         synd[0x8];
3728 	u8         ext_synd[0x10];
3729 };
3730 
3731 struct mlx5_ifc_register_loopback_control_bits {
3732 	u8         no_lb[0x1];
3733 	u8         reserved_0[0x7];
3734 	u8         port[0x8];
3735 	u8         reserved_1[0x10];
3736 
3737 	u8         reserved_2[0x60];
3738 };
3739 
3740 struct mlx5_ifc_lrh_bits {
3741 	u8	vl[4];
3742 	u8	lver[4];
3743 	u8	sl[4];
3744 	u8	reserved2[2];
3745 	u8	lnh[2];
3746 	u8	dlid[16];
3747 	u8	reserved5[5];
3748 	u8	pkt_len[11];
3749 	u8	slid[16];
3750 };
3751 
3752 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3753 	u8         reserved_0[0x40];
3754 
3755 	u8         reserved_1[0x10];
3756 	u8         rol_mode[0x8];
3757 	u8         wol_mode[0x8];
3758 };
3759 
3760 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3761 	u8         reserved_0[0x40];
3762 
3763 	u8         rol_mode_valid[0x1];
3764 	u8         wol_mode_valid[0x1];
3765 	u8         reserved_1[0xe];
3766 	u8         rol_mode[0x8];
3767 	u8         wol_mode[0x8];
3768 
3769 	u8         reserved_2[0x7a0];
3770 };
3771 
3772 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3773 	u8         virtual_mac_en[0x1];
3774 	u8         mac_aux_v[0x1];
3775 	u8         reserved_0[0x1e];
3776 
3777 	u8         reserved_1[0x40];
3778 
3779 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3780 
3781 	u8         reserved_2[0x760];
3782 };
3783 
3784 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3785 	u8         virtual_mac_en[0x1];
3786 	u8         mac_aux_v[0x1];
3787 	u8         reserved_0[0x1e];
3788 
3789 	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3790 
3791 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3792 
3793 	u8         reserved_1[0x760];
3794 };
3795 
3796 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3797 	struct mlx5_ifc_fw_version_bits fw_version;
3798 
3799 	u8         reserved_0[0x10];
3800 	u8         hash_signature[0x10];
3801 
3802 	u8         psid[16][0x8];
3803 
3804 	u8         reserved_1[0x6e0];
3805 };
3806 
3807 struct mlx5_ifc_icmd_query_cap_in_bits {
3808 	u8         reserved_0[0x10];
3809 	u8         capability_group[0x10];
3810 };
3811 
3812 struct mlx5_ifc_icmd_query_cap_general_bits {
3813 	u8         nv_access[0x1];
3814 	u8         fw_info_psid[0x1];
3815 	u8         reserved_0[0x1e];
3816 
3817 	u8         reserved_1[0x16];
3818 	u8         rol_s[0x1];
3819 	u8         rol_g[0x1];
3820 	u8         reserved_2[0x1];
3821 	u8         wol_s[0x1];
3822 	u8         wol_g[0x1];
3823 	u8         wol_a[0x1];
3824 	u8         wol_b[0x1];
3825 	u8         wol_m[0x1];
3826 	u8         wol_u[0x1];
3827 	u8         wol_p[0x1];
3828 };
3829 
3830 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3831 	u8         status[0x8];
3832 	u8         reserved_0[0x18];
3833 
3834 	u8         reserved_1[0x7e0];
3835 };
3836 
3837 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3838 	u8         status[0x8];
3839 	u8         reserved_0[0x18];
3840 
3841 	u8         reserved_1[0x7e0];
3842 };
3843 
3844 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3845 	u8         address_hi[0x20];
3846 
3847 	u8         address_lo[0x20];
3848 
3849 	u8         reserved_0[0x7c0];
3850 };
3851 
3852 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3853 	u8         reserved_0[0x20];
3854 
3855 	u8         address_hi[0x20];
3856 
3857 	u8         address_lo[0x20];
3858 
3859 	u8         reserved_1[0x7a0];
3860 };
3861 
3862 struct mlx5_ifc_icmd_access_reg_out_bits {
3863 	u8         reserved_0[0x11];
3864 	u8         status[0x7];
3865 	u8         reserved_1[0x8];
3866 
3867 	u8         register_id[0x10];
3868 	u8         reserved_2[0x10];
3869 
3870 	u8         reserved_3[0x40];
3871 
3872 	u8         reserved_4[0x5];
3873 	u8         len[0xb];
3874 	u8         reserved_5[0x10];
3875 
3876 	u8         register_data[0][0x20];
3877 };
3878 
3879 enum {
3880 	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3881 	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3882 };
3883 
3884 struct mlx5_ifc_icmd_access_reg_in_bits {
3885 	u8         constant_1[0x5];
3886 	u8         constant_2[0xb];
3887 	u8         reserved_0[0x10];
3888 
3889 	u8         register_id[0x10];
3890 	u8         reserved_1[0x1];
3891 	u8         method[0x7];
3892 	u8         constant_3[0x8];
3893 
3894 	u8         reserved_2[0x40];
3895 
3896 	u8         constant_4[0x5];
3897 	u8         len[0xb];
3898 	u8         reserved_3[0x10];
3899 
3900 	u8         register_data[0][0x20];
3901 };
3902 
3903 enum {
3904 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3905 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3906 };
3907 
3908 struct mlx5_ifc_teardown_hca_out_bits {
3909 	u8         status[0x8];
3910 	u8         reserved_0[0x18];
3911 
3912 	u8         syndrome[0x20];
3913 
3914 	u8         reserved_1[0x3f];
3915 
3916 	u8	   state[0x1];
3917 };
3918 
3919 enum {
3920 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3921 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3922 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3923 };
3924 
3925 struct mlx5_ifc_teardown_hca_in_bits {
3926 	u8         opcode[0x10];
3927 	u8         reserved_0[0x10];
3928 
3929 	u8         reserved_1[0x10];
3930 	u8         op_mod[0x10];
3931 
3932 	u8         reserved_2[0x10];
3933 	u8         profile[0x10];
3934 
3935 	u8         reserved_3[0x20];
3936 };
3937 
3938 struct mlx5_ifc_set_delay_drop_params_out_bits {
3939 	u8         status[0x8];
3940 	u8         reserved_at_8[0x18];
3941 
3942 	u8         syndrome[0x20];
3943 
3944 	u8         reserved_at_40[0x40];
3945 };
3946 
3947 struct mlx5_ifc_set_delay_drop_params_in_bits {
3948 	u8         opcode[0x10];
3949 	u8         reserved_at_10[0x10];
3950 
3951 	u8         reserved_at_20[0x10];
3952 	u8         op_mod[0x10];
3953 
3954 	u8         reserved_at_40[0x20];
3955 
3956 	u8         reserved_at_60[0x10];
3957 	u8         delay_drop_timeout[0x10];
3958 };
3959 
3960 struct mlx5_ifc_query_delay_drop_params_out_bits {
3961 	u8         status[0x8];
3962 	u8         reserved_at_8[0x18];
3963 
3964 	u8         syndrome[0x20];
3965 
3966 	u8         reserved_at_40[0x20];
3967 
3968 	u8         reserved_at_60[0x10];
3969 	u8         delay_drop_timeout[0x10];
3970 };
3971 
3972 struct mlx5_ifc_query_delay_drop_params_in_bits {
3973 	u8         opcode[0x10];
3974 	u8         reserved_at_10[0x10];
3975 
3976 	u8         reserved_at_20[0x10];
3977 	u8         op_mod[0x10];
3978 
3979 	u8         reserved_at_40[0x40];
3980 };
3981 
3982 struct mlx5_ifc_suspend_qp_out_bits {
3983 	u8         status[0x8];
3984 	u8         reserved_0[0x18];
3985 
3986 	u8         syndrome[0x20];
3987 
3988 	u8         reserved_1[0x40];
3989 };
3990 
3991 struct mlx5_ifc_suspend_qp_in_bits {
3992 	u8         opcode[0x10];
3993 	u8         reserved_0[0x10];
3994 
3995 	u8         reserved_1[0x10];
3996 	u8         op_mod[0x10];
3997 
3998 	u8         reserved_2[0x8];
3999 	u8         qpn[0x18];
4000 
4001 	u8         reserved_3[0x20];
4002 };
4003 
4004 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4005 	u8         status[0x8];
4006 	u8         reserved_0[0x18];
4007 
4008 	u8         syndrome[0x20];
4009 
4010 	u8         reserved_1[0x40];
4011 };
4012 
4013 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4014 	u8         opcode[0x10];
4015 	u8         uid[0x10];
4016 
4017 	u8         reserved_1[0x10];
4018 	u8         op_mod[0x10];
4019 
4020 	u8         reserved_2[0x8];
4021 	u8         qpn[0x18];
4022 
4023 	u8         reserved_3[0x20];
4024 
4025 	u8         opt_param_mask[0x20];
4026 
4027 	u8         reserved_4[0x20];
4028 
4029 	struct mlx5_ifc_qpc_bits qpc;
4030 
4031 	u8         reserved_5[0x80];
4032 };
4033 
4034 struct mlx5_ifc_sqd2rts_qp_out_bits {
4035 	u8         status[0x8];
4036 	u8         reserved_0[0x18];
4037 
4038 	u8         syndrome[0x20];
4039 
4040 	u8         reserved_1[0x40];
4041 };
4042 
4043 struct mlx5_ifc_sqd2rts_qp_in_bits {
4044 	u8         opcode[0x10];
4045 	u8         uid[0x10];
4046 
4047 	u8         reserved_1[0x10];
4048 	u8         op_mod[0x10];
4049 
4050 	u8         reserved_2[0x8];
4051 	u8         qpn[0x18];
4052 
4053 	u8         reserved_3[0x20];
4054 
4055 	u8         opt_param_mask[0x20];
4056 
4057 	u8         reserved_4[0x20];
4058 
4059 	struct mlx5_ifc_qpc_bits qpc;
4060 
4061 	u8         reserved_5[0x80];
4062 };
4063 
4064 struct mlx5_ifc_set_wol_rol_out_bits {
4065 	u8         status[0x8];
4066 	u8         reserved_0[0x18];
4067 
4068 	u8         syndrome[0x20];
4069 
4070 	u8         reserved_1[0x40];
4071 };
4072 
4073 struct mlx5_ifc_set_wol_rol_in_bits {
4074 	u8         opcode[0x10];
4075 	u8         reserved_0[0x10];
4076 
4077 	u8         reserved_1[0x10];
4078 	u8         op_mod[0x10];
4079 
4080 	u8         rol_mode_valid[0x1];
4081 	u8         wol_mode_valid[0x1];
4082 	u8         reserved_2[0xe];
4083 	u8         rol_mode[0x8];
4084 	u8         wol_mode[0x8];
4085 
4086 	u8         reserved_3[0x20];
4087 };
4088 
4089 struct mlx5_ifc_set_roce_address_out_bits {
4090 	u8         status[0x8];
4091 	u8         reserved_0[0x18];
4092 
4093 	u8         syndrome[0x20];
4094 
4095 	u8         reserved_1[0x40];
4096 };
4097 
4098 struct mlx5_ifc_set_roce_address_in_bits {
4099 	u8         opcode[0x10];
4100 	u8         reserved_0[0x10];
4101 
4102 	u8         reserved_1[0x10];
4103 	u8         op_mod[0x10];
4104 
4105 	u8         roce_address_index[0x10];
4106 	u8         reserved_2[0x10];
4107 
4108 	u8         reserved_3[0x20];
4109 
4110 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4111 };
4112 
4113 struct mlx5_ifc_set_rdb_out_bits {
4114 	u8         status[0x8];
4115 	u8         reserved_0[0x18];
4116 
4117 	u8         syndrome[0x20];
4118 
4119 	u8         reserved_1[0x40];
4120 };
4121 
4122 struct mlx5_ifc_set_rdb_in_bits {
4123 	u8         opcode[0x10];
4124 	u8         reserved_0[0x10];
4125 
4126 	u8         reserved_1[0x10];
4127 	u8         op_mod[0x10];
4128 
4129 	u8         reserved_2[0x8];
4130 	u8         qpn[0x18];
4131 
4132 	u8         reserved_3[0x18];
4133 	u8         rdb_list_size[0x8];
4134 
4135 	struct mlx5_ifc_rdbc_bits rdb_context[0];
4136 };
4137 
4138 struct mlx5_ifc_set_mad_demux_out_bits {
4139 	u8         status[0x8];
4140 	u8         reserved_0[0x18];
4141 
4142 	u8         syndrome[0x20];
4143 
4144 	u8         reserved_1[0x40];
4145 };
4146 
4147 enum {
4148 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4149 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4150 };
4151 
4152 struct mlx5_ifc_set_mad_demux_in_bits {
4153 	u8         opcode[0x10];
4154 	u8         reserved_0[0x10];
4155 
4156 	u8         reserved_1[0x10];
4157 	u8         op_mod[0x10];
4158 
4159 	u8         reserved_2[0x20];
4160 
4161 	u8         reserved_3[0x6];
4162 	u8         demux_mode[0x2];
4163 	u8         reserved_4[0x18];
4164 };
4165 
4166 struct mlx5_ifc_set_l2_table_entry_out_bits {
4167 	u8         status[0x8];
4168 	u8         reserved_0[0x18];
4169 
4170 	u8         syndrome[0x20];
4171 
4172 	u8         reserved_1[0x40];
4173 };
4174 
4175 struct mlx5_ifc_set_l2_table_entry_in_bits {
4176 	u8         opcode[0x10];
4177 	u8         reserved_0[0x10];
4178 
4179 	u8         reserved_1[0x10];
4180 	u8         op_mod[0x10];
4181 
4182 	u8         reserved_2[0x60];
4183 
4184 	u8         reserved_3[0x8];
4185 	u8         table_index[0x18];
4186 
4187 	u8         reserved_4[0x20];
4188 
4189 	u8         reserved_5[0x13];
4190 	u8         vlan_valid[0x1];
4191 	u8         vlan[0xc];
4192 
4193 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4194 
4195 	u8         reserved_6[0xc0];
4196 };
4197 
4198 struct mlx5_ifc_set_issi_out_bits {
4199 	u8         status[0x8];
4200 	u8         reserved_0[0x18];
4201 
4202 	u8         syndrome[0x20];
4203 
4204 	u8         reserved_1[0x40];
4205 };
4206 
4207 struct mlx5_ifc_set_issi_in_bits {
4208 	u8         opcode[0x10];
4209 	u8         reserved_0[0x10];
4210 
4211 	u8         reserved_1[0x10];
4212 	u8         op_mod[0x10];
4213 
4214 	u8         reserved_2[0x10];
4215 	u8         current_issi[0x10];
4216 
4217 	u8         reserved_3[0x20];
4218 };
4219 
4220 struct mlx5_ifc_set_hca_cap_out_bits {
4221 	u8         status[0x8];
4222 	u8         reserved_0[0x18];
4223 
4224 	u8         syndrome[0x20];
4225 
4226 	u8         reserved_1[0x40];
4227 };
4228 
4229 struct mlx5_ifc_set_hca_cap_in_bits {
4230 	u8         opcode[0x10];
4231 	u8         reserved_0[0x10];
4232 
4233 	u8         reserved_1[0x10];
4234 	u8         op_mod[0x10];
4235 
4236 	u8         reserved_2[0x40];
4237 
4238 	union mlx5_ifc_hca_cap_union_bits capability;
4239 };
4240 
4241 enum {
4242 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
4243 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
4244 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
4245 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
4246 };
4247 
4248 struct mlx5_ifc_set_flow_table_root_out_bits {
4249 	u8         status[0x8];
4250 	u8         reserved_0[0x18];
4251 
4252 	u8         syndrome[0x20];
4253 
4254 	u8         reserved_1[0x40];
4255 };
4256 
4257 struct mlx5_ifc_set_flow_table_root_in_bits {
4258         u8         opcode[0x10];
4259         u8         reserved_at_10[0x10];
4260 
4261         u8         reserved_at_20[0x10];
4262         u8         op_mod[0x10];
4263 
4264         u8         other_vport[0x1];
4265         u8         reserved_at_41[0xf];
4266         u8         vport_number[0x10];
4267 
4268         u8         reserved_at_60[0x20];
4269 
4270         u8         table_type[0x8];
4271         u8         reserved_at_88[0x7];
4272         u8         table_of_other_vport[0x1];
4273         u8         table_vport_number[0x10];
4274 
4275         u8         reserved_at_a0[0x8];
4276         u8         table_id[0x18];
4277 
4278         u8         reserved_at_c0[0x8];
4279         u8         underlay_qpn[0x18];
4280         u8         table_eswitch_owner_vhca_id_valid[0x1];
4281         u8         reserved_at_e1[0xf];
4282         u8         table_eswitch_owner_vhca_id[0x10];
4283         u8         reserved_at_100[0x100];
4284 };
4285 
4286 struct mlx5_ifc_set_fte_out_bits {
4287 	u8         status[0x8];
4288 	u8         reserved_0[0x18];
4289 
4290 	u8         syndrome[0x20];
4291 
4292 	u8         reserved_1[0x40];
4293 };
4294 
4295 struct mlx5_ifc_set_fte_in_bits {
4296         u8         opcode[0x10];
4297         u8         reserved_at_10[0x10];
4298 
4299         u8         reserved_at_20[0x10];
4300         u8         op_mod[0x10];
4301 
4302         u8         other_vport[0x1];
4303         u8         reserved_at_41[0xf];
4304         u8         vport_number[0x10];
4305 
4306         u8         reserved_at_60[0x20];
4307 
4308         u8         table_type[0x8];
4309         u8         reserved_at_88[0x18];
4310 
4311         u8         reserved_at_a0[0x8];
4312         u8         table_id[0x18];
4313 
4314         u8         ignore_flow_level[0x1];
4315         u8         reserved_at_c1[0x17];
4316         u8         modify_enable_mask[0x8];
4317 
4318         u8         reserved_at_e0[0x20];
4319 
4320         u8         flow_index[0x20];
4321 
4322         u8         reserved_at_120[0xe0];
4323 
4324         struct mlx5_ifc_flow_context_bits flow_context;
4325 };
4326 
4327 struct mlx5_ifc_set_driver_version_out_bits {
4328 	u8         status[0x8];
4329 	u8         reserved_0[0x18];
4330 
4331 	u8         syndrome[0x20];
4332 
4333 	u8         reserved_1[0x40];
4334 };
4335 
4336 struct mlx5_ifc_set_driver_version_in_bits {
4337 	u8         opcode[0x10];
4338 	u8         reserved_0[0x10];
4339 
4340 	u8         reserved_1[0x10];
4341 	u8         op_mod[0x10];
4342 
4343 	u8         reserved_2[0x40];
4344 
4345 	u8         driver_version[64][0x8];
4346 };
4347 
4348 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
4349 	u8         status[0x8];
4350 	u8         reserved_0[0x18];
4351 
4352 	u8         syndrome[0x20];
4353 
4354 	u8         reserved_1[0x40];
4355 };
4356 
4357 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
4358 	u8         opcode[0x10];
4359 	u8         reserved_0[0x10];
4360 
4361 	u8         reserved_1[0x10];
4362 	u8         op_mod[0x10];
4363 
4364 	u8         enable[0x1];
4365 	u8         reserved_2[0x1f];
4366 
4367 	u8         reserved_3[0x160];
4368 
4369 	struct mlx5_ifc_cmd_pas_bits pas;
4370 };
4371 
4372 struct mlx5_ifc_set_burst_size_out_bits {
4373 	u8         status[0x8];
4374 	u8         reserved_0[0x18];
4375 
4376 	u8         syndrome[0x20];
4377 
4378 	u8         reserved_1[0x40];
4379 };
4380 
4381 struct mlx5_ifc_set_burst_size_in_bits {
4382 	u8         opcode[0x10];
4383 	u8         reserved_0[0x10];
4384 
4385 	u8         reserved_1[0x10];
4386 	u8         op_mod[0x10];
4387 
4388 	u8         reserved_2[0x20];
4389 
4390 	u8         reserved_3[0x9];
4391 	u8         device_burst_size[0x17];
4392 };
4393 
4394 struct mlx5_ifc_rts2rts_qp_out_bits {
4395 	u8         status[0x8];
4396 	u8         reserved_0[0x18];
4397 
4398 	u8         syndrome[0x20];
4399 
4400 	u8         reserved_1[0x40];
4401 };
4402 
4403 struct mlx5_ifc_rts2rts_qp_in_bits {
4404 	u8         opcode[0x10];
4405 	u8         uid[0x10];
4406 
4407 	u8         reserved_1[0x10];
4408 	u8         op_mod[0x10];
4409 
4410 	u8         reserved_2[0x8];
4411 	u8         qpn[0x18];
4412 
4413 	u8         reserved_3[0x20];
4414 
4415 	u8         opt_param_mask[0x20];
4416 
4417 	u8         reserved_4[0x20];
4418 
4419 	struct mlx5_ifc_qpc_bits qpc;
4420 
4421 	u8         reserved_5[0x80];
4422 };
4423 
4424 struct mlx5_ifc_rtr2rts_qp_out_bits {
4425 	u8         status[0x8];
4426 	u8         reserved_0[0x18];
4427 
4428 	u8         syndrome[0x20];
4429 
4430 	u8         reserved_1[0x40];
4431 };
4432 
4433 struct mlx5_ifc_rtr2rts_qp_in_bits {
4434 	u8         opcode[0x10];
4435 	u8         uid[0x10];
4436 
4437 	u8         reserved_1[0x10];
4438 	u8         op_mod[0x10];
4439 
4440 	u8         reserved_2[0x8];
4441 	u8         qpn[0x18];
4442 
4443 	u8         reserved_3[0x20];
4444 
4445 	u8         opt_param_mask[0x20];
4446 
4447 	u8         reserved_4[0x20];
4448 
4449 	struct mlx5_ifc_qpc_bits qpc;
4450 
4451 	u8         reserved_5[0x80];
4452 };
4453 
4454 struct mlx5_ifc_rst2init_qp_out_bits {
4455 	u8         status[0x8];
4456 	u8         reserved_0[0x18];
4457 
4458 	u8         syndrome[0x20];
4459 
4460 	u8         reserved_1[0x40];
4461 };
4462 
4463 struct mlx5_ifc_rst2init_qp_in_bits {
4464 	u8         opcode[0x10];
4465 	u8         uid[0x10];
4466 
4467 	u8         reserved_1[0x10];
4468 	u8         op_mod[0x10];
4469 
4470 	u8         reserved_2[0x8];
4471 	u8         qpn[0x18];
4472 
4473 	u8         reserved_3[0x20];
4474 
4475 	u8         opt_param_mask[0x20];
4476 
4477 	u8         reserved_4[0x20];
4478 
4479 	struct mlx5_ifc_qpc_bits qpc;
4480 
4481 	u8         reserved_5[0x80];
4482 };
4483 
4484 struct mlx5_ifc_query_xrq_out_bits {
4485 	u8         status[0x8];
4486 	u8         reserved_at_8[0x18];
4487 
4488 	u8         syndrome[0x20];
4489 
4490 	u8         reserved_at_40[0x40];
4491 
4492 	struct mlx5_ifc_xrqc_bits xrq_context;
4493 };
4494 
4495 struct mlx5_ifc_query_xrq_in_bits {
4496 	u8         opcode[0x10];
4497 	u8         reserved_at_10[0x10];
4498 
4499 	u8         reserved_at_20[0x10];
4500 	u8         op_mod[0x10];
4501 
4502 	u8         reserved_at_40[0x8];
4503 	u8         xrqn[0x18];
4504 
4505 	u8         reserved_at_60[0x20];
4506 };
4507 
4508 struct mlx5_ifc_resume_qp_out_bits {
4509 	u8         status[0x8];
4510 	u8         reserved_0[0x18];
4511 
4512 	u8         syndrome[0x20];
4513 
4514 	u8         reserved_1[0x40];
4515 };
4516 
4517 struct mlx5_ifc_resume_qp_in_bits {
4518 	u8         opcode[0x10];
4519 	u8         reserved_0[0x10];
4520 
4521 	u8         reserved_1[0x10];
4522 	u8         op_mod[0x10];
4523 
4524 	u8         reserved_2[0x8];
4525 	u8         qpn[0x18];
4526 
4527 	u8         reserved_3[0x20];
4528 };
4529 
4530 struct mlx5_ifc_query_xrc_srq_out_bits {
4531 	u8         status[0x8];
4532 	u8         reserved_0[0x18];
4533 
4534 	u8         syndrome[0x20];
4535 
4536 	u8         reserved_1[0x40];
4537 
4538 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4539 
4540 	u8         reserved_2[0x600];
4541 
4542 	u8         pas[0][0x40];
4543 };
4544 
4545 struct mlx5_ifc_query_xrc_srq_in_bits {
4546 	u8         opcode[0x10];
4547 	u8         uid[0x10];
4548 
4549 	u8         reserved_1[0x10];
4550 	u8         op_mod[0x10];
4551 
4552 	u8         reserved_2[0x8];
4553 	u8         xrc_srqn[0x18];
4554 
4555 	u8         reserved_3[0x20];
4556 };
4557 
4558 struct mlx5_ifc_query_wol_rol_out_bits {
4559 	u8         status[0x8];
4560 	u8         reserved_0[0x18];
4561 
4562 	u8         syndrome[0x20];
4563 
4564 	u8         reserved_1[0x10];
4565 	u8         rol_mode[0x8];
4566 	u8         wol_mode[0x8];
4567 
4568 	u8         reserved_2[0x20];
4569 };
4570 
4571 struct mlx5_ifc_query_wol_rol_in_bits {
4572 	u8         opcode[0x10];
4573 	u8         reserved_0[0x10];
4574 
4575 	u8         reserved_1[0x10];
4576 	u8         op_mod[0x10];
4577 
4578 	u8         reserved_2[0x40];
4579 };
4580 
4581 enum {
4582 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4583 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4584 };
4585 
4586 struct mlx5_ifc_query_vport_state_out_bits {
4587 	u8         status[0x8];
4588 	u8         reserved_0[0x18];
4589 
4590 	u8         syndrome[0x20];
4591 
4592 	u8         reserved_1[0x20];
4593 
4594 	u8         reserved_2[0x18];
4595 	u8         admin_state[0x4];
4596 	u8         state[0x4];
4597 };
4598 
4599 enum {
4600 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4601 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4602 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4603 };
4604 
4605 enum {
4606         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
4607         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
4608         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
4609         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
4610         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
4611         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
4612         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
4613         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
4614         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
4615         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
4616         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
4617         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
4618         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
4619         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
4620 };
4621 
4622 struct mlx5_ifc_query_vport_state_in_bits {
4623 	u8         opcode[0x10];
4624 	u8         reserved_0[0x10];
4625 
4626 	u8         reserved_1[0x10];
4627 	u8         op_mod[0x10];
4628 
4629 	u8         other_vport[0x1];
4630 	u8         reserved_2[0xf];
4631 	u8         vport_number[0x10];
4632 
4633 	u8         reserved_3[0x20];
4634 };
4635 
4636 struct mlx5_ifc_query_vnic_env_out_bits {
4637 	u8         status[0x8];
4638 	u8         reserved_at_8[0x18];
4639 
4640 	u8         syndrome[0x20];
4641 
4642 	u8         reserved_at_40[0x40];
4643 
4644 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4645 };
4646 
4647 enum {
4648 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4649 };
4650 
4651 struct mlx5_ifc_query_vnic_env_in_bits {
4652 	u8         opcode[0x10];
4653 	u8         reserved_at_10[0x10];
4654 
4655 	u8         reserved_at_20[0x10];
4656 	u8         op_mod[0x10];
4657 
4658 	u8         other_vport[0x1];
4659 	u8         reserved_at_41[0xf];
4660 	u8         vport_number[0x10];
4661 
4662 	u8         reserved_at_60[0x20];
4663 };
4664 
4665 struct mlx5_ifc_query_vport_counter_out_bits {
4666 	u8         status[0x8];
4667 	u8         reserved_0[0x18];
4668 
4669 	u8         syndrome[0x20];
4670 
4671 	u8         reserved_1[0x40];
4672 
4673 	struct mlx5_ifc_traffic_counter_bits received_errors;
4674 
4675 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4676 
4677 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4678 
4679 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4680 
4681 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4682 
4683 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4684 
4685 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4686 
4687 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4688 
4689 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4690 
4691 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4692 
4693 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4694 
4695 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4696 
4697 	u8         reserved_2[0xa00];
4698 };
4699 
4700 enum {
4701 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4702 };
4703 
4704 struct mlx5_ifc_query_vport_counter_in_bits {
4705 	u8         opcode[0x10];
4706 	u8         reserved_0[0x10];
4707 
4708 	u8         reserved_1[0x10];
4709 	u8         op_mod[0x10];
4710 
4711 	u8         other_vport[0x1];
4712 	u8         reserved_2[0xb];
4713 	u8         port_num[0x4];
4714 	u8         vport_number[0x10];
4715 
4716 	u8         reserved_3[0x60];
4717 
4718 	u8         clear[0x1];
4719 	u8         reserved_4[0x1f];
4720 
4721 	u8         reserved_5[0x20];
4722 };
4723 
4724 struct mlx5_ifc_query_tis_out_bits {
4725 	u8         status[0x8];
4726 	u8         reserved_0[0x18];
4727 
4728 	u8         syndrome[0x20];
4729 
4730 	u8         reserved_1[0x40];
4731 
4732 	struct mlx5_ifc_tisc_bits tis_context;
4733 };
4734 
4735 struct mlx5_ifc_query_tis_in_bits {
4736 	u8         opcode[0x10];
4737 	u8         reserved_0[0x10];
4738 
4739 	u8         reserved_1[0x10];
4740 	u8         op_mod[0x10];
4741 
4742 	u8         reserved_2[0x8];
4743 	u8         tisn[0x18];
4744 
4745 	u8         reserved_3[0x20];
4746 };
4747 
4748 struct mlx5_ifc_query_tir_out_bits {
4749 	u8         status[0x8];
4750 	u8         reserved_0[0x18];
4751 
4752 	u8         syndrome[0x20];
4753 
4754 	u8         reserved_1[0xc0];
4755 
4756 	struct mlx5_ifc_tirc_bits tir_context;
4757 };
4758 
4759 struct mlx5_ifc_query_tir_in_bits {
4760 	u8         opcode[0x10];
4761 	u8         reserved_0[0x10];
4762 
4763 	u8         reserved_1[0x10];
4764 	u8         op_mod[0x10];
4765 
4766 	u8         reserved_2[0x8];
4767 	u8         tirn[0x18];
4768 
4769 	u8         reserved_3[0x20];
4770 };
4771 
4772 struct mlx5_ifc_query_srq_out_bits {
4773 	u8         status[0x8];
4774 	u8         reserved_0[0x18];
4775 
4776 	u8         syndrome[0x20];
4777 
4778 	u8         reserved_1[0x40];
4779 
4780 	struct mlx5_ifc_srqc_bits srq_context_entry;
4781 
4782 	u8         reserved_2[0x600];
4783 
4784 	u8         pas[0][0x40];
4785 };
4786 
4787 struct mlx5_ifc_query_srq_in_bits {
4788 	u8         opcode[0x10];
4789 	u8         reserved_0[0x10];
4790 
4791 	u8         reserved_1[0x10];
4792 	u8         op_mod[0x10];
4793 
4794 	u8         reserved_2[0x8];
4795 	u8         srqn[0x18];
4796 
4797 	u8         reserved_3[0x20];
4798 };
4799 
4800 struct mlx5_ifc_query_sq_out_bits {
4801 	u8         status[0x8];
4802 	u8         reserved_0[0x18];
4803 
4804 	u8         syndrome[0x20];
4805 
4806 	u8         reserved_1[0xc0];
4807 
4808 	struct mlx5_ifc_sqc_bits sq_context;
4809 };
4810 
4811 struct mlx5_ifc_query_sq_in_bits {
4812 	u8         opcode[0x10];
4813 	u8         reserved_0[0x10];
4814 
4815 	u8         reserved_1[0x10];
4816 	u8         op_mod[0x10];
4817 
4818 	u8         reserved_2[0x8];
4819 	u8         sqn[0x18];
4820 
4821 	u8         reserved_3[0x20];
4822 };
4823 
4824 struct mlx5_ifc_query_special_contexts_out_bits {
4825 	u8         status[0x8];
4826 	u8         reserved_0[0x18];
4827 
4828 	u8         syndrome[0x20];
4829 
4830 	u8	   dump_fill_mkey[0x20];
4831 
4832 	u8         resd_lkey[0x20];
4833 };
4834 
4835 struct mlx5_ifc_query_special_contexts_in_bits {
4836 	u8         opcode[0x10];
4837 	u8         reserved_0[0x10];
4838 
4839 	u8         reserved_1[0x10];
4840 	u8         op_mod[0x10];
4841 
4842 	u8         reserved_2[0x40];
4843 };
4844 
4845 struct mlx5_ifc_query_scheduling_element_out_bits {
4846 	u8         status[0x8];
4847 	u8         reserved_at_8[0x18];
4848 
4849 	u8         syndrome[0x20];
4850 
4851 	u8         reserved_at_40[0xc0];
4852 
4853 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4854 
4855 	u8         reserved_at_300[0x100];
4856 };
4857 
4858 enum {
4859 	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4860 };
4861 
4862 struct mlx5_ifc_query_scheduling_element_in_bits {
4863 	u8         opcode[0x10];
4864 	u8         reserved_at_10[0x10];
4865 
4866 	u8         reserved_at_20[0x10];
4867 	u8         op_mod[0x10];
4868 
4869 	u8         scheduling_hierarchy[0x8];
4870 	u8         reserved_at_48[0x18];
4871 
4872 	u8         scheduling_element_id[0x20];
4873 
4874 	u8         reserved_at_80[0x180];
4875 };
4876 
4877 struct mlx5_ifc_query_rqt_out_bits {
4878 	u8         status[0x8];
4879 	u8         reserved_0[0x18];
4880 
4881 	u8         syndrome[0x20];
4882 
4883 	u8         reserved_1[0xc0];
4884 
4885 	struct mlx5_ifc_rqtc_bits rqt_context;
4886 };
4887 
4888 struct mlx5_ifc_query_rqt_in_bits {
4889 	u8         opcode[0x10];
4890 	u8         reserved_0[0x10];
4891 
4892 	u8         reserved_1[0x10];
4893 	u8         op_mod[0x10];
4894 
4895 	u8         reserved_2[0x8];
4896 	u8         rqtn[0x18];
4897 
4898 	u8         reserved_3[0x20];
4899 };
4900 
4901 struct mlx5_ifc_query_rq_out_bits {
4902 	u8         status[0x8];
4903 	u8         reserved_0[0x18];
4904 
4905 	u8         syndrome[0x20];
4906 
4907 	u8         reserved_1[0xc0];
4908 
4909 	struct mlx5_ifc_rqc_bits rq_context;
4910 };
4911 
4912 struct mlx5_ifc_query_rq_in_bits {
4913 	u8         opcode[0x10];
4914 	u8         reserved_0[0x10];
4915 
4916 	u8         reserved_1[0x10];
4917 	u8         op_mod[0x10];
4918 
4919 	u8         reserved_2[0x8];
4920 	u8         rqn[0x18];
4921 
4922 	u8         reserved_3[0x20];
4923 };
4924 
4925 struct mlx5_ifc_query_roce_address_out_bits {
4926 	u8         status[0x8];
4927 	u8         reserved_0[0x18];
4928 
4929 	u8         syndrome[0x20];
4930 
4931 	u8         reserved_1[0x40];
4932 
4933 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4934 };
4935 
4936 struct mlx5_ifc_query_roce_address_in_bits {
4937 	u8         opcode[0x10];
4938 	u8         reserved_0[0x10];
4939 
4940 	u8         reserved_1[0x10];
4941 	u8         op_mod[0x10];
4942 
4943 	u8         roce_address_index[0x10];
4944 	u8         reserved_2[0x10];
4945 
4946 	u8         reserved_3[0x20];
4947 };
4948 
4949 struct mlx5_ifc_query_rmp_out_bits {
4950 	u8         status[0x8];
4951 	u8         reserved_0[0x18];
4952 
4953 	u8         syndrome[0x20];
4954 
4955 	u8         reserved_1[0xc0];
4956 
4957 	struct mlx5_ifc_rmpc_bits rmp_context;
4958 };
4959 
4960 struct mlx5_ifc_query_rmp_in_bits {
4961 	u8         opcode[0x10];
4962 	u8         reserved_0[0x10];
4963 
4964 	u8         reserved_1[0x10];
4965 	u8         op_mod[0x10];
4966 
4967 	u8         reserved_2[0x8];
4968 	u8         rmpn[0x18];
4969 
4970 	u8         reserved_3[0x20];
4971 };
4972 
4973 struct mlx5_ifc_query_rdb_out_bits {
4974 	u8         status[0x8];
4975 	u8         reserved_0[0x18];
4976 
4977 	u8         syndrome[0x20];
4978 
4979 	u8         reserved_1[0x20];
4980 
4981 	u8         reserved_2[0x18];
4982 	u8         rdb_list_size[0x8];
4983 
4984 	struct mlx5_ifc_rdbc_bits rdb_context[0];
4985 };
4986 
4987 struct mlx5_ifc_query_rdb_in_bits {
4988 	u8         opcode[0x10];
4989 	u8         reserved_0[0x10];
4990 
4991 	u8         reserved_1[0x10];
4992 	u8         op_mod[0x10];
4993 
4994 	u8         reserved_2[0x8];
4995 	u8         qpn[0x18];
4996 
4997 	u8         reserved_3[0x20];
4998 };
4999 
5000 struct mlx5_ifc_query_qp_out_bits {
5001 	u8         status[0x8];
5002 	u8         reserved_0[0x18];
5003 
5004 	u8         syndrome[0x20];
5005 
5006 	u8         reserved_1[0x40];
5007 
5008 	u8         opt_param_mask[0x20];
5009 
5010 	u8         reserved_2[0x20];
5011 
5012 	struct mlx5_ifc_qpc_bits qpc;
5013 
5014 	u8         reserved_3[0x80];
5015 
5016 	u8         pas[0][0x40];
5017 };
5018 
5019 struct mlx5_ifc_query_qp_in_bits {
5020 	u8         opcode[0x10];
5021 	u8         reserved_0[0x10];
5022 
5023 	u8         reserved_1[0x10];
5024 	u8         op_mod[0x10];
5025 
5026 	u8         reserved_2[0x8];
5027 	u8         qpn[0x18];
5028 
5029 	u8         reserved_3[0x20];
5030 };
5031 
5032 struct mlx5_ifc_query_q_counter_out_bits {
5033 	u8         status[0x8];
5034 	u8         reserved_0[0x18];
5035 
5036 	u8         syndrome[0x20];
5037 
5038 	u8         reserved_1[0x40];
5039 
5040 	u8         rx_write_requests[0x20];
5041 
5042 	u8         reserved_2[0x20];
5043 
5044 	u8         rx_read_requests[0x20];
5045 
5046 	u8         reserved_3[0x20];
5047 
5048 	u8         rx_atomic_requests[0x20];
5049 
5050 	u8         reserved_4[0x20];
5051 
5052 	u8         rx_dct_connect[0x20];
5053 
5054 	u8         reserved_5[0x20];
5055 
5056 	u8         out_of_buffer[0x20];
5057 
5058 	u8         reserved_7[0x20];
5059 
5060 	u8         out_of_sequence[0x20];
5061 
5062 	u8         reserved_8[0x20];
5063 
5064 	u8         duplicate_request[0x20];
5065 
5066 	u8         reserved_9[0x20];
5067 
5068 	u8         rnr_nak_retry_err[0x20];
5069 
5070 	u8         reserved_10[0x20];
5071 
5072 	u8         packet_seq_err[0x20];
5073 
5074 	u8         reserved_11[0x20];
5075 
5076 	u8         implied_nak_seq_err[0x20];
5077 
5078 	u8         reserved_12[0x20];
5079 
5080 	u8         local_ack_timeout_err[0x20];
5081 
5082 	u8         reserved_13[0x20];
5083 
5084 	u8         resp_rnr_nak[0x20];
5085 
5086 	u8         reserved_14[0x20];
5087 
5088 	u8         req_rnr_retries_exceeded[0x20];
5089 
5090 	u8         reserved_15[0x460];
5091 };
5092 
5093 struct mlx5_ifc_query_q_counter_in_bits {
5094 	u8         opcode[0x10];
5095 	u8         reserved_0[0x10];
5096 
5097 	u8         reserved_1[0x10];
5098 	u8         op_mod[0x10];
5099 
5100 	u8         reserved_2[0x80];
5101 
5102 	u8         clear[0x1];
5103 	u8         reserved_3[0x1f];
5104 
5105 	u8         reserved_4[0x18];
5106 	u8         counter_set_id[0x8];
5107 };
5108 
5109 struct mlx5_ifc_query_pages_out_bits {
5110 	u8         status[0x8];
5111 	u8         reserved_0[0x18];
5112 
5113 	u8         syndrome[0x20];
5114 
5115 	u8         reserved_1[0x10];
5116 	u8         function_id[0x10];
5117 
5118 	u8         num_pages[0x20];
5119 };
5120 
5121 enum {
5122 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
5123 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
5124 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5125 };
5126 
5127 struct mlx5_ifc_query_pages_in_bits {
5128 	u8         opcode[0x10];
5129 	u8         reserved_0[0x10];
5130 
5131 	u8         reserved_1[0x10];
5132 	u8         op_mod[0x10];
5133 
5134 	u8         reserved_2[0x10];
5135 	u8         function_id[0x10];
5136 
5137 	u8         reserved_3[0x20];
5138 };
5139 
5140 struct mlx5_ifc_query_nic_vport_context_out_bits {
5141 	u8         status[0x8];
5142 	u8         reserved_0[0x18];
5143 
5144 	u8         syndrome[0x20];
5145 
5146 	u8         reserved_1[0x40];
5147 
5148 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5149 };
5150 
5151 struct mlx5_ifc_query_nic_vport_context_in_bits {
5152 	u8         opcode[0x10];
5153 	u8         reserved_0[0x10];
5154 
5155 	u8         reserved_1[0x10];
5156 	u8         op_mod[0x10];
5157 
5158 	u8         other_vport[0x1];
5159 	u8         reserved_2[0xf];
5160 	u8         vport_number[0x10];
5161 
5162 	u8         reserved_3[0x5];
5163 	u8         allowed_list_type[0x3];
5164 	u8         reserved_4[0x18];
5165 };
5166 
5167 struct mlx5_ifc_query_mkey_out_bits {
5168 	u8         status[0x8];
5169 	u8         reserved_0[0x18];
5170 
5171 	u8         syndrome[0x20];
5172 
5173 	u8         reserved_1[0x40];
5174 
5175 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5176 
5177 	u8         reserved_2[0x600];
5178 
5179 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5180 
5181 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5182 };
5183 
5184 struct mlx5_ifc_query_mkey_in_bits {
5185 	u8         opcode[0x10];
5186 	u8         reserved_0[0x10];
5187 
5188 	u8         reserved_1[0x10];
5189 	u8         op_mod[0x10];
5190 
5191 	u8         reserved_2[0x8];
5192 	u8         mkey_index[0x18];
5193 
5194 	u8         pg_access[0x1];
5195 	u8         reserved_3[0x1f];
5196 };
5197 
5198 struct mlx5_ifc_query_mad_demux_out_bits {
5199 	u8         status[0x8];
5200 	u8         reserved_0[0x18];
5201 
5202 	u8         syndrome[0x20];
5203 
5204 	u8         reserved_1[0x40];
5205 
5206 	u8         mad_dumux_parameters_block[0x20];
5207 };
5208 
5209 struct mlx5_ifc_query_mad_demux_in_bits {
5210 	u8         opcode[0x10];
5211 	u8         reserved_0[0x10];
5212 
5213 	u8         reserved_1[0x10];
5214 	u8         op_mod[0x10];
5215 
5216 	u8         reserved_2[0x40];
5217 };
5218 
5219 struct mlx5_ifc_query_l2_table_entry_out_bits {
5220 	u8         status[0x8];
5221 	u8         reserved_0[0x18];
5222 
5223 	u8         syndrome[0x20];
5224 
5225 	u8         reserved_1[0xa0];
5226 
5227 	u8         reserved_2[0x13];
5228 	u8         vlan_valid[0x1];
5229 	u8         vlan[0xc];
5230 
5231 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5232 
5233 	u8         reserved_3[0xc0];
5234 };
5235 
5236 struct mlx5_ifc_query_l2_table_entry_in_bits {
5237 	u8         opcode[0x10];
5238 	u8         reserved_0[0x10];
5239 
5240 	u8         reserved_1[0x10];
5241 	u8         op_mod[0x10];
5242 
5243 	u8         reserved_2[0x60];
5244 
5245 	u8         reserved_3[0x8];
5246 	u8         table_index[0x18];
5247 
5248 	u8         reserved_4[0x140];
5249 };
5250 
5251 struct mlx5_ifc_query_issi_out_bits {
5252 	u8         status[0x8];
5253 	u8         reserved_0[0x18];
5254 
5255 	u8         syndrome[0x20];
5256 
5257 	u8         reserved_1[0x10];
5258 	u8         current_issi[0x10];
5259 
5260 	u8         reserved_2[0xa0];
5261 
5262 	u8         supported_issi_reserved[76][0x8];
5263 	u8         supported_issi_dw0[0x20];
5264 };
5265 
5266 struct mlx5_ifc_query_issi_in_bits {
5267 	u8         opcode[0x10];
5268 	u8         reserved_0[0x10];
5269 
5270 	u8         reserved_1[0x10];
5271 	u8         op_mod[0x10];
5272 
5273 	u8         reserved_2[0x40];
5274 };
5275 
5276 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5277 	u8         status[0x8];
5278 	u8         reserved_0[0x18];
5279 
5280 	u8         syndrome[0x20];
5281 
5282 	u8         reserved_1[0x40];
5283 
5284 	struct mlx5_ifc_pkey_bits pkey[0];
5285 };
5286 
5287 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5288 	u8         opcode[0x10];
5289 	u8         reserved_0[0x10];
5290 
5291 	u8         reserved_1[0x10];
5292 	u8         op_mod[0x10];
5293 
5294 	u8         other_vport[0x1];
5295 	u8         reserved_2[0xb];
5296 	u8         port_num[0x4];
5297 	u8         vport_number[0x10];
5298 
5299 	u8         reserved_3[0x10];
5300 	u8         pkey_index[0x10];
5301 };
5302 
5303 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5304 	u8         status[0x8];
5305 	u8         reserved_0[0x18];
5306 
5307 	u8         syndrome[0x20];
5308 
5309 	u8         reserved_1[0x20];
5310 
5311 	u8         gids_num[0x10];
5312 	u8         reserved_2[0x10];
5313 
5314 	struct mlx5_ifc_array128_auto_bits gid[0];
5315 };
5316 
5317 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5318 	u8         opcode[0x10];
5319 	u8         reserved_0[0x10];
5320 
5321 	u8         reserved_1[0x10];
5322 	u8         op_mod[0x10];
5323 
5324 	u8         other_vport[0x1];
5325 	u8         reserved_2[0xb];
5326 	u8         port_num[0x4];
5327 	u8         vport_number[0x10];
5328 
5329 	u8         reserved_3[0x10];
5330 	u8         gid_index[0x10];
5331 };
5332 
5333 struct mlx5_ifc_query_hca_vport_context_out_bits {
5334 	u8         status[0x8];
5335 	u8         reserved_0[0x18];
5336 
5337 	u8         syndrome[0x20];
5338 
5339 	u8         reserved_1[0x40];
5340 
5341 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5342 };
5343 
5344 struct mlx5_ifc_query_hca_vport_context_in_bits {
5345 	u8         opcode[0x10];
5346 	u8         reserved_0[0x10];
5347 
5348 	u8         reserved_1[0x10];
5349 	u8         op_mod[0x10];
5350 
5351 	u8         other_vport[0x1];
5352 	u8         reserved_2[0xb];
5353 	u8         port_num[0x4];
5354 	u8         vport_number[0x10];
5355 
5356 	u8         reserved_3[0x20];
5357 };
5358 
5359 struct mlx5_ifc_query_hca_cap_out_bits {
5360 	u8         status[0x8];
5361 	u8         reserved_0[0x18];
5362 
5363 	u8         syndrome[0x20];
5364 
5365 	u8         reserved_1[0x40];
5366 
5367 	union mlx5_ifc_hca_cap_union_bits capability;
5368 };
5369 
5370 struct mlx5_ifc_query_hca_cap_in_bits {
5371 	u8         opcode[0x10];
5372 	u8         reserved_0[0x10];
5373 
5374 	u8         reserved_1[0x10];
5375 	u8         op_mod[0x10];
5376 
5377 	u8         reserved_2[0x40];
5378 };
5379 
5380 struct mlx5_ifc_query_flow_table_out_bits {
5381 	u8         status[0x8];
5382 	u8         reserved_at_8[0x18];
5383 
5384 	u8         syndrome[0x20];
5385 
5386 	u8         reserved_at_40[0x80];
5387 
5388 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5389 };
5390 
5391 struct mlx5_ifc_query_flow_table_in_bits {
5392 	u8         opcode[0x10];
5393 	u8         reserved_0[0x10];
5394 
5395 	u8         reserved_1[0x10];
5396 	u8         op_mod[0x10];
5397 
5398 	u8         other_vport[0x1];
5399 	u8         reserved_2[0xf];
5400 	u8         vport_number[0x10];
5401 
5402 	u8         reserved_3[0x20];
5403 
5404 	u8         table_type[0x8];
5405 	u8         reserved_4[0x18];
5406 
5407 	u8         reserved_5[0x8];
5408 	u8         table_id[0x18];
5409 
5410 	u8         reserved_6[0x140];
5411 };
5412 
5413 struct mlx5_ifc_query_fte_out_bits {
5414 	u8         status[0x8];
5415 	u8         reserved_0[0x18];
5416 
5417 	u8         syndrome[0x20];
5418 
5419 	u8         reserved_1[0x1c0];
5420 
5421 	struct mlx5_ifc_flow_context_bits flow_context;
5422 };
5423 
5424 struct mlx5_ifc_query_fte_in_bits {
5425 	u8         opcode[0x10];
5426 	u8         reserved_0[0x10];
5427 
5428 	u8         reserved_1[0x10];
5429 	u8         op_mod[0x10];
5430 
5431 	u8         other_vport[0x1];
5432 	u8         reserved_2[0xf];
5433 	u8         vport_number[0x10];
5434 
5435 	u8         reserved_3[0x20];
5436 
5437 	u8         table_type[0x8];
5438 	u8         reserved_4[0x18];
5439 
5440 	u8         reserved_5[0x8];
5441 	u8         table_id[0x18];
5442 
5443 	u8         reserved_6[0x40];
5444 
5445 	u8         flow_index[0x20];
5446 
5447 	u8         reserved_7[0xe0];
5448 };
5449 
5450 enum {
5451 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5452 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5453 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5454 };
5455 
5456 struct mlx5_ifc_query_flow_group_out_bits {
5457 	u8         status[0x8];
5458 	u8         reserved_0[0x18];
5459 
5460 	u8         syndrome[0x20];
5461 
5462 	u8         reserved_1[0xa0];
5463 
5464 	u8         start_flow_index[0x20];
5465 
5466 	u8         reserved_2[0x20];
5467 
5468 	u8         end_flow_index[0x20];
5469 
5470 	u8         reserved_3[0xa0];
5471 
5472 	u8         reserved_4[0x18];
5473 	u8         match_criteria_enable[0x8];
5474 
5475 	struct mlx5_ifc_fte_match_param_bits match_criteria;
5476 
5477 	u8         reserved_5[0xe00];
5478 };
5479 
5480 struct mlx5_ifc_query_flow_group_in_bits {
5481 	u8         opcode[0x10];
5482 	u8         reserved_0[0x10];
5483 
5484 	u8         reserved_1[0x10];
5485 	u8         op_mod[0x10];
5486 
5487 	u8         other_vport[0x1];
5488 	u8         reserved_2[0xf];
5489 	u8         vport_number[0x10];
5490 
5491 	u8         reserved_3[0x20];
5492 
5493 	u8         table_type[0x8];
5494 	u8         reserved_4[0x18];
5495 
5496 	u8         reserved_5[0x8];
5497 	u8         table_id[0x18];
5498 
5499 	u8         group_id[0x20];
5500 
5501 	u8         reserved_6[0x120];
5502 };
5503 
5504 struct mlx5_ifc_query_flow_counter_out_bits {
5505 	u8         status[0x8];
5506 	u8         reserved_at_8[0x18];
5507 
5508 	u8         syndrome[0x20];
5509 
5510 	u8         reserved_at_40[0x40];
5511 
5512 	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5513 };
5514 
5515 struct mlx5_ifc_query_flow_counter_in_bits {
5516 	u8         opcode[0x10];
5517 	u8         reserved_at_10[0x10];
5518 
5519 	u8         reserved_at_20[0x10];
5520 	u8         op_mod[0x10];
5521 
5522 	u8         reserved_at_40[0x80];
5523 
5524 	u8         clear[0x1];
5525 	u8         reserved_at_c1[0xf];
5526 	u8         num_of_counters[0x10];
5527 
5528 	u8         reserved_at_e0[0x10];
5529 	u8         flow_counter_id[0x10];
5530 };
5531 
5532 struct mlx5_ifc_query_esw_vport_context_out_bits {
5533 	u8         status[0x8];
5534 	u8         reserved_0[0x18];
5535 
5536 	u8         syndrome[0x20];
5537 
5538 	u8         reserved_1[0x40];
5539 
5540 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5541 };
5542 
5543 struct mlx5_ifc_query_esw_vport_context_in_bits {
5544 	u8         opcode[0x10];
5545 	u8         reserved_0[0x10];
5546 
5547 	u8         reserved_1[0x10];
5548 	u8         op_mod[0x10];
5549 
5550 	u8         other_vport[0x1];
5551 	u8         reserved_2[0xf];
5552 	u8         vport_number[0x10];
5553 
5554 	u8         reserved_3[0x20];
5555 };
5556 
5557 struct mlx5_ifc_query_eq_out_bits {
5558 	u8         status[0x8];
5559 	u8         reserved_0[0x18];
5560 
5561 	u8         syndrome[0x20];
5562 
5563 	u8         reserved_1[0x40];
5564 
5565 	struct mlx5_ifc_eqc_bits eq_context_entry;
5566 
5567 	u8         reserved_2[0x40];
5568 
5569 	u8         event_bitmask[0x40];
5570 
5571 	u8         reserved_3[0x580];
5572 
5573 	u8         pas[0][0x40];
5574 };
5575 
5576 struct mlx5_ifc_query_eq_in_bits {
5577 	u8         opcode[0x10];
5578 	u8         reserved_0[0x10];
5579 
5580 	u8         reserved_1[0x10];
5581 	u8         op_mod[0x10];
5582 
5583 	u8         reserved_2[0x18];
5584 	u8         eq_number[0x8];
5585 
5586 	u8         reserved_3[0x20];
5587 };
5588 
5589 struct mlx5_ifc_set_action_in_bits {
5590         u8         action_type[0x4];
5591         u8         field[0xc];
5592         u8         reserved_at_10[0x3];
5593         u8         offset[0x5];
5594         u8         reserved_at_18[0x3];
5595         u8         length[0x5];
5596 
5597         u8         data[0x20];
5598 };
5599 
5600 struct mlx5_ifc_add_action_in_bits {
5601         u8         action_type[0x4];
5602         u8         field[0xc];
5603         u8         reserved_at_10[0x10];
5604 
5605         u8         data[0x20];
5606 };
5607 
5608 struct mlx5_ifc_copy_action_in_bits {
5609         u8         action_type[0x4];
5610         u8         src_field[0xc];
5611         u8         reserved_at_10[0x3];
5612         u8         src_offset[0x5];
5613         u8         reserved_at_18[0x3];
5614         u8         length[0x5];
5615 
5616         u8         reserved_at_20[0x4];
5617         u8         dst_field[0xc];
5618         u8         reserved_at_30[0x3];
5619         u8         dst_offset[0x5];
5620         u8         reserved_at_38[0x8];
5621 };
5622 
5623 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5624         struct mlx5_ifc_set_action_in_bits  set_action_in;
5625         struct mlx5_ifc_add_action_in_bits  add_action_in;
5626         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5627         u8         reserved_at_0[0x40];
5628 };
5629 
5630 enum {
5631         MLX5_ACTION_TYPE_SET   = 0x1,
5632         MLX5_ACTION_TYPE_ADD   = 0x2,
5633         MLX5_ACTION_TYPE_COPY  = 0x3,
5634 };
5635 
5636 enum {
5637         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5638         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5639         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5640         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5641         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5642         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5643         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5644         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5645         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5646         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5647         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5648         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5649         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5650         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5651         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5652         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5653         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5654         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5655         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5656         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5657         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5658         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5659         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5660         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5661         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5662         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5663         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5664         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5665         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5666         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5667         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5668         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5669         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5670         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5671         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5672         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5673         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
5674         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
5675         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
5676 };
5677 
5678 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5679         u8         status[0x8];
5680         u8         reserved_at_8[0x18];
5681 
5682         u8         syndrome[0x20];
5683 
5684         u8         modify_header_id[0x20];
5685 
5686         u8         reserved_at_60[0x20];
5687 };
5688 
5689 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5690         u8         opcode[0x10];
5691         u8         reserved_at_10[0x10];
5692 
5693         u8         reserved_at_20[0x10];
5694         u8         op_mod[0x10];
5695 
5696         u8         reserved_at_40[0x20];
5697 
5698         u8         table_type[0x8];
5699         u8         reserved_at_68[0x10];
5700         u8         num_of_actions[0x8];
5701 
5702         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5703 };
5704 
5705 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708 
5709         u8         syndrome[0x20];
5710 
5711         u8         reserved_at_40[0x40];
5712 };
5713 
5714 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5715         u8         opcode[0x10];
5716         u8         reserved_at_10[0x10];
5717 
5718         u8         reserved_at_20[0x10];
5719         u8         op_mod[0x10];
5720 
5721         u8         modify_header_id[0x20];
5722 
5723         u8         reserved_at_60[0x20];
5724 };
5725 
5726 struct mlx5_ifc_query_modify_header_context_in_bits {
5727         u8         opcode[0x10];
5728         u8         uid[0x10];
5729 
5730         u8         reserved_at_20[0x10];
5731         u8         op_mod[0x10];
5732 
5733         u8         modify_header_id[0x20];
5734 
5735         u8         reserved_at_60[0xa0];
5736 };
5737 
5738 struct mlx5_ifc_query_dct_out_bits {
5739 	u8         status[0x8];
5740 	u8         reserved_0[0x18];
5741 
5742 	u8         syndrome[0x20];
5743 
5744 	u8         reserved_1[0x40];
5745 
5746 	struct mlx5_ifc_dctc_bits dct_context_entry;
5747 
5748 	u8         reserved_2[0x180];
5749 };
5750 
5751 struct mlx5_ifc_query_dct_in_bits {
5752 	u8         opcode[0x10];
5753 	u8         reserved_0[0x10];
5754 
5755 	u8         reserved_1[0x10];
5756 	u8         op_mod[0x10];
5757 
5758 	u8         reserved_2[0x8];
5759 	u8         dctn[0x18];
5760 
5761 	u8         reserved_3[0x20];
5762 };
5763 
5764 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5765 	u8         status[0x8];
5766 	u8         reserved_0[0x18];
5767 
5768 	u8         syndrome[0x20];
5769 
5770 	u8         enable[0x1];
5771 	u8         reserved_1[0x1f];
5772 
5773 	u8         reserved_2[0x160];
5774 
5775 	struct mlx5_ifc_cmd_pas_bits pas;
5776 };
5777 
5778 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5779 	u8         opcode[0x10];
5780 	u8         reserved_0[0x10];
5781 
5782 	u8         reserved_1[0x10];
5783 	u8         op_mod[0x10];
5784 
5785 	u8         reserved_2[0x40];
5786 };
5787 
5788 struct mlx5_ifc_packet_reformat_context_in_bits {
5789         u8         reformat_type[0x8];
5790         u8         reserved_at_8[0x4];
5791         u8         reformat_param_0[0x4];
5792         u8         reserved_at_10[0x6];
5793         u8         reformat_data_size[0xa];
5794 
5795         u8         reformat_param_1[0x8];
5796         u8         reserved_at_28[0x8];
5797         u8         reformat_data[2][0x8];
5798 
5799         u8         more_reformat_data[][0x8];
5800 };
5801 
5802 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5803 	u8         status[0x8];
5804 	u8         reserved_at_8[0x18];
5805 
5806 	u8         syndrome[0x20];
5807 
5808 	u8         reserved_at_40[0xa0];
5809 
5810 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5811 };
5812 
5813 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5814 	u8         opcode[0x10];
5815 	u8         reserved_at_10[0x10];
5816 
5817 	u8         reserved_at_20[0x10];
5818 	u8         op_mod[0x10];
5819 
5820 	u8         packet_reformat_id[0x20];
5821 
5822 	u8         reserved_at_60[0xa0];
5823 };
5824 
5825 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5826 	u8         status[0x8];
5827 	u8         reserved_at_8[0x18];
5828 
5829 	u8         syndrome[0x20];
5830 
5831 	u8         packet_reformat_id[0x20];
5832 
5833 	u8         reserved_at_60[0x20];
5834 };
5835 
5836 enum mlx5_reformat_ctx_type {
5837 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5838 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5839 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5840 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5841 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5842 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
5843 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
5844 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
5845 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
5846 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
5847 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
5848 };
5849 
5850 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5851 	u8         opcode[0x10];
5852 	u8         reserved_at_10[0x10];
5853 
5854 	u8         reserved_at_20[0x10];
5855 	u8         op_mod[0x10];
5856 
5857 	u8         reserved_at_40[0xa0];
5858 
5859 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5860 };
5861 
5862 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5863 	u8         status[0x8];
5864 	u8         reserved_at_8[0x18];
5865 
5866 	u8         syndrome[0x20];
5867 
5868 	u8         reserved_at_40[0x40];
5869 };
5870 
5871 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5872 	u8         opcode[0x10];
5873 	u8         reserved_at_10[0x10];
5874 
5875 	u8         reserved_20[0x10];
5876 	u8         op_mod[0x10];
5877 
5878 	u8         packet_reformat_id[0x20];
5879 
5880 	u8         reserved_60[0x20];
5881 };
5882 
5883 struct mlx5_ifc_diagnostic_cntr_struct_bits {
5884 	u8         counter_id[0x10];
5885 	u8         sample_id[0x10];
5886 
5887 	u8         time_stamp_31_0[0x20];
5888 
5889 	u8         counter_value_h[0x20];
5890 
5891 	u8         counter_value_l[0x20];
5892 };
5893 
5894 enum {
5895 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE   = 0x1,
5896 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE  = 0x0,
5897 };
5898 
5899 struct mlx5_ifc_query_cq_out_bits {
5900 	u8         status[0x8];
5901 	u8         reserved_0[0x18];
5902 
5903 	u8         syndrome[0x20];
5904 
5905 	u8         reserved_1[0x40];
5906 
5907 	struct mlx5_ifc_cqc_bits cq_context;
5908 
5909 	u8         reserved_2[0x600];
5910 
5911 	u8         pas[0][0x40];
5912 };
5913 
5914 struct mlx5_ifc_query_cq_in_bits {
5915 	u8         opcode[0x10];
5916 	u8         reserved_0[0x10];
5917 
5918 	u8         reserved_1[0x10];
5919 	u8         op_mod[0x10];
5920 
5921 	u8         reserved_2[0x8];
5922 	u8         cqn[0x18];
5923 
5924 	u8         reserved_3[0x20];
5925 };
5926 
5927 struct mlx5_ifc_query_cong_status_out_bits {
5928 	u8         status[0x8];
5929 	u8         reserved_0[0x18];
5930 
5931 	u8         syndrome[0x20];
5932 
5933 	u8         reserved_1[0x20];
5934 
5935 	u8         enable[0x1];
5936 	u8         tag_enable[0x1];
5937 	u8         reserved_2[0x1e];
5938 };
5939 
5940 struct mlx5_ifc_query_cong_status_in_bits {
5941 	u8         opcode[0x10];
5942 	u8         reserved_0[0x10];
5943 
5944 	u8         reserved_1[0x10];
5945 	u8         op_mod[0x10];
5946 
5947 	u8         reserved_2[0x18];
5948 	u8         priority[0x4];
5949 	u8         cong_protocol[0x4];
5950 
5951 	u8         reserved_3[0x20];
5952 };
5953 
5954 struct mlx5_ifc_query_cong_statistics_out_bits {
5955 	u8         status[0x8];
5956 	u8         reserved_0[0x18];
5957 
5958 	u8         syndrome[0x20];
5959 
5960 	u8         reserved_1[0x40];
5961 
5962 	u8         rp_cur_flows[0x20];
5963 
5964 	u8         sum_flows[0x20];
5965 
5966 	u8         rp_cnp_ignored_high[0x20];
5967 
5968 	u8         rp_cnp_ignored_low[0x20];
5969 
5970 	u8         rp_cnp_handled_high[0x20];
5971 
5972 	u8         rp_cnp_handled_low[0x20];
5973 
5974 	u8         reserved_2[0x100];
5975 
5976 	u8         time_stamp_high[0x20];
5977 
5978 	u8         time_stamp_low[0x20];
5979 
5980 	u8         accumulators_period[0x20];
5981 
5982 	u8         np_ecn_marked_roce_packets_high[0x20];
5983 
5984 	u8         np_ecn_marked_roce_packets_low[0x20];
5985 
5986 	u8         np_cnp_sent_high[0x20];
5987 
5988 	u8         np_cnp_sent_low[0x20];
5989 
5990 	u8         reserved_3[0x560];
5991 };
5992 
5993 struct mlx5_ifc_query_cong_statistics_in_bits {
5994 	u8         opcode[0x10];
5995 	u8         reserved_0[0x10];
5996 
5997 	u8         reserved_1[0x10];
5998 	u8         op_mod[0x10];
5999 
6000 	u8         clear[0x1];
6001 	u8         reserved_2[0x1f];
6002 
6003 	u8         reserved_3[0x20];
6004 };
6005 
6006 struct mlx5_ifc_query_cong_params_out_bits {
6007 	u8         status[0x8];
6008 	u8         reserved_0[0x18];
6009 
6010 	u8         syndrome[0x20];
6011 
6012 	u8         reserved_1[0x40];
6013 
6014 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6015 };
6016 
6017 struct mlx5_ifc_query_cong_params_in_bits {
6018 	u8         opcode[0x10];
6019 	u8         reserved_0[0x10];
6020 
6021 	u8         reserved_1[0x10];
6022 	u8         op_mod[0x10];
6023 
6024 	u8         reserved_2[0x1c];
6025 	u8         cong_protocol[0x4];
6026 
6027 	u8         reserved_3[0x20];
6028 };
6029 
6030 struct mlx5_ifc_query_burst_size_out_bits {
6031 	u8         status[0x8];
6032 	u8         reserved_0[0x18];
6033 
6034 	u8         syndrome[0x20];
6035 
6036 	u8         reserved_1[0x20];
6037 
6038 	u8         reserved_2[0x9];
6039 	u8         device_burst_size[0x17];
6040 };
6041 
6042 struct mlx5_ifc_query_burst_size_in_bits {
6043 	u8         opcode[0x10];
6044 	u8         reserved_0[0x10];
6045 
6046 	u8         reserved_1[0x10];
6047 	u8         op_mod[0x10];
6048 
6049 	u8         reserved_2[0x40];
6050 };
6051 
6052 struct mlx5_ifc_query_adapter_out_bits {
6053 	u8         status[0x8];
6054 	u8         reserved_0[0x18];
6055 
6056 	u8         syndrome[0x20];
6057 
6058 	u8         reserved_1[0x40];
6059 
6060 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6061 };
6062 
6063 struct mlx5_ifc_query_adapter_in_bits {
6064 	u8         opcode[0x10];
6065 	u8         reserved_0[0x10];
6066 
6067 	u8         reserved_1[0x10];
6068 	u8         op_mod[0x10];
6069 
6070 	u8         reserved_2[0x40];
6071 };
6072 
6073 struct mlx5_ifc_qp_2rst_out_bits {
6074 	u8         status[0x8];
6075 	u8         reserved_0[0x18];
6076 
6077 	u8         syndrome[0x20];
6078 
6079 	u8         reserved_1[0x40];
6080 };
6081 
6082 struct mlx5_ifc_qp_2rst_in_bits {
6083 	u8         opcode[0x10];
6084 	u8         uid[0x10];
6085 
6086 	u8         reserved_1[0x10];
6087 	u8         op_mod[0x10];
6088 
6089 	u8         reserved_2[0x8];
6090 	u8         qpn[0x18];
6091 
6092 	u8         reserved_3[0x20];
6093 };
6094 
6095 struct mlx5_ifc_qp_2err_out_bits {
6096 	u8         status[0x8];
6097 	u8         reserved_0[0x18];
6098 
6099 	u8         syndrome[0x20];
6100 
6101 	u8         reserved_1[0x40];
6102 };
6103 
6104 struct mlx5_ifc_qp_2err_in_bits {
6105 	u8         opcode[0x10];
6106 	u8         uid[0x10];
6107 
6108 	u8         reserved_1[0x10];
6109 	u8         op_mod[0x10];
6110 
6111 	u8         reserved_2[0x8];
6112 	u8         qpn[0x18];
6113 
6114 	u8         reserved_3[0x20];
6115 };
6116 
6117 struct mlx5_ifc_para_vport_element_bits {
6118 	u8         reserved_at_0[0xc];
6119 	u8         traffic_class[0x4];
6120 	u8         qos_para_vport_number[0x10];
6121 };
6122 
6123 struct mlx5_ifc_page_fault_resume_out_bits {
6124 	u8         status[0x8];
6125 	u8         reserved_0[0x18];
6126 
6127 	u8         syndrome[0x20];
6128 
6129 	u8         reserved_1[0x40];
6130 };
6131 
6132 struct mlx5_ifc_page_fault_resume_in_bits {
6133 	u8         opcode[0x10];
6134 	u8         reserved_0[0x10];
6135 
6136 	u8         reserved_1[0x10];
6137 	u8         op_mod[0x10];
6138 
6139 	u8         error[0x1];
6140 	u8         reserved_2[0x4];
6141 	u8         rdma[0x1];
6142 	u8         read_write[0x1];
6143 	u8         req_res[0x1];
6144 	u8         qpn[0x18];
6145 
6146 	u8         reserved_3[0x20];
6147 };
6148 
6149 struct mlx5_ifc_nop_out_bits {
6150 	u8         status[0x8];
6151 	u8         reserved_0[0x18];
6152 
6153 	u8         syndrome[0x20];
6154 
6155 	u8         reserved_1[0x40];
6156 };
6157 
6158 struct mlx5_ifc_nop_in_bits {
6159 	u8         opcode[0x10];
6160 	u8         reserved_0[0x10];
6161 
6162 	u8         reserved_1[0x10];
6163 	u8         op_mod[0x10];
6164 
6165 	u8         reserved_2[0x40];
6166 };
6167 
6168 struct mlx5_ifc_modify_vport_state_out_bits {
6169 	u8         status[0x8];
6170 	u8         reserved_0[0x18];
6171 
6172 	u8         syndrome[0x20];
6173 
6174 	u8         reserved_1[0x40];
6175 };
6176 
6177 enum {
6178 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
6179 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
6180 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
6181 };
6182 
6183 enum {
6184 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
6185 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
6186 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
6187 };
6188 
6189 struct mlx5_ifc_modify_vport_state_in_bits {
6190 	u8         opcode[0x10];
6191 	u8         reserved_0[0x10];
6192 
6193 	u8         reserved_1[0x10];
6194 	u8         op_mod[0x10];
6195 
6196 	u8         other_vport[0x1];
6197 	u8         reserved_2[0xf];
6198 	u8         vport_number[0x10];
6199 
6200 	u8         reserved_3[0x18];
6201 	u8         admin_state[0x4];
6202 	u8         reserved_4[0x4];
6203 };
6204 
6205 struct mlx5_ifc_modify_tis_out_bits {
6206 	u8         status[0x8];
6207 	u8         reserved_0[0x18];
6208 
6209 	u8         syndrome[0x20];
6210 
6211 	u8         reserved_1[0x40];
6212 };
6213 
6214 struct mlx5_ifc_modify_tis_bitmask_bits {
6215 	u8         reserved_at_0[0x20];
6216 
6217 	u8         reserved_at_20[0x1d];
6218 	u8         lag_tx_port_affinity[0x1];
6219 	u8         strict_lag_tx_port_affinity[0x1];
6220 	u8         prio[0x1];
6221 };
6222 
6223 struct mlx5_ifc_modify_tis_in_bits {
6224 	u8         opcode[0x10];
6225 	u8         uid[0x10];
6226 
6227 	u8         reserved_1[0x10];
6228 	u8         op_mod[0x10];
6229 
6230 	u8         reserved_2[0x8];
6231 	u8         tisn[0x18];
6232 
6233 	u8         reserved_3[0x20];
6234 
6235 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6236 
6237 	u8         reserved_4[0x40];
6238 
6239 	struct mlx5_ifc_tisc_bits ctx;
6240 };
6241 
6242 struct mlx5_ifc_modify_tir_out_bits {
6243 	u8         status[0x8];
6244 	u8         reserved_0[0x18];
6245 
6246 	u8         syndrome[0x20];
6247 
6248 	u8         reserved_1[0x40];
6249 };
6250 
6251 enum
6252 {
6253 	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
6254 	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
6255 };
6256 
6257 struct mlx5_ifc_modify_tir_in_bits {
6258 	u8         opcode[0x10];
6259 	u8         uid[0x10];
6260 
6261 	u8         reserved_1[0x10];
6262 	u8         op_mod[0x10];
6263 
6264 	u8         reserved_2[0x8];
6265 	u8         tirn[0x18];
6266 
6267 	u8         reserved_3[0x20];
6268 
6269 	u8         modify_bitmask[0x40];
6270 
6271 	u8         reserved_4[0x40];
6272 
6273 	struct mlx5_ifc_tirc_bits tir_context;
6274 };
6275 
6276 struct mlx5_ifc_modify_sq_out_bits {
6277 	u8         status[0x8];
6278 	u8         reserved_0[0x18];
6279 
6280 	u8         syndrome[0x20];
6281 
6282 	u8         reserved_1[0x40];
6283 };
6284 
6285 struct mlx5_ifc_modify_sq_in_bits {
6286 	u8         opcode[0x10];
6287 	u8         uid[0x10];
6288 
6289 	u8         reserved_1[0x10];
6290 	u8         op_mod[0x10];
6291 
6292 	u8         sq_state[0x4];
6293 	u8         reserved_2[0x4];
6294 	u8         sqn[0x18];
6295 
6296 	u8         reserved_3[0x20];
6297 
6298 	u8         modify_bitmask[0x40];
6299 
6300 	u8         reserved_4[0x40];
6301 
6302 	struct mlx5_ifc_sqc_bits ctx;
6303 };
6304 
6305 struct mlx5_ifc_modify_scheduling_element_out_bits {
6306 	u8         status[0x8];
6307 	u8         reserved_at_8[0x18];
6308 
6309 	u8         syndrome[0x20];
6310 
6311 	u8         reserved_at_40[0x1c0];
6312 };
6313 
6314 enum {
6315 	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6316 };
6317 
6318 enum {
6319 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
6320 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
6321 };
6322 
6323 struct mlx5_ifc_modify_scheduling_element_in_bits {
6324 	u8         opcode[0x10];
6325 	u8         reserved_at_10[0x10];
6326 
6327 	u8         reserved_at_20[0x10];
6328 	u8         op_mod[0x10];
6329 
6330 	u8         scheduling_hierarchy[0x8];
6331 	u8         reserved_at_48[0x18];
6332 
6333 	u8         scheduling_element_id[0x20];
6334 
6335 	u8         reserved_at_80[0x20];
6336 
6337 	u8         modify_bitmask[0x20];
6338 
6339 	u8         reserved_at_c0[0x40];
6340 
6341 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6342 
6343 	u8         reserved_at_300[0x100];
6344 };
6345 
6346 struct mlx5_ifc_modify_rqt_out_bits {
6347 	u8         status[0x8];
6348 	u8         reserved_0[0x18];
6349 
6350 	u8         syndrome[0x20];
6351 
6352 	u8         reserved_1[0x40];
6353 };
6354 
6355 struct mlx5_ifc_rqt_bitmask_bits {
6356 	u8         reserved_at_0[0x20];
6357 
6358 	u8         reserved_at_20[0x1f];
6359 	u8         rqn_list[0x1];
6360 };
6361 
6362 
6363 struct mlx5_ifc_modify_rqt_in_bits {
6364 	u8         opcode[0x10];
6365 	u8         uid[0x10];
6366 
6367 	u8         reserved_1[0x10];
6368 	u8         op_mod[0x10];
6369 
6370 	u8         reserved_2[0x8];
6371 	u8         rqtn[0x18];
6372 
6373 	u8         reserved_3[0x20];
6374 
6375 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
6376 
6377 	u8         reserved_4[0x40];
6378 
6379 	struct mlx5_ifc_rqtc_bits ctx;
6380 };
6381 
6382 struct mlx5_ifc_modify_rq_out_bits {
6383 	u8         status[0x8];
6384 	u8         reserved_0[0x18];
6385 
6386 	u8         syndrome[0x20];
6387 
6388 	u8         reserved_1[0x40];
6389 };
6390 
6391 enum {
6392 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6393 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
6394 };
6395 
6396 struct mlx5_ifc_modify_rq_in_bits {
6397 	u8         opcode[0x10];
6398 	u8         uid[0x10];
6399 
6400 	u8         reserved_1[0x10];
6401 	u8         op_mod[0x10];
6402 
6403 	u8         rq_state[0x4];
6404 	u8         reserved_2[0x4];
6405 	u8         rqn[0x18];
6406 
6407 	u8         reserved_3[0x20];
6408 
6409 	u8         modify_bitmask[0x40];
6410 
6411 	u8         reserved_4[0x40];
6412 
6413 	struct mlx5_ifc_rqc_bits ctx;
6414 };
6415 
6416 struct mlx5_ifc_modify_rmp_out_bits {
6417 	u8         status[0x8];
6418 	u8         reserved_0[0x18];
6419 
6420 	u8         syndrome[0x20];
6421 
6422 	u8         reserved_1[0x40];
6423 };
6424 
6425 struct mlx5_ifc_rmp_bitmask_bits {
6426 	u8	   reserved[0x20];
6427 
6428 	u8         reserved1[0x1f];
6429 	u8         lwm[0x1];
6430 };
6431 
6432 struct mlx5_ifc_modify_rmp_in_bits {
6433 	u8         opcode[0x10];
6434 	u8         uid[0x10];
6435 
6436 	u8         reserved_1[0x10];
6437 	u8         op_mod[0x10];
6438 
6439 	u8         rmp_state[0x4];
6440 	u8         reserved_2[0x4];
6441 	u8         rmpn[0x18];
6442 
6443 	u8         reserved_3[0x20];
6444 
6445 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
6446 
6447 	u8         reserved_4[0x40];
6448 
6449 	struct mlx5_ifc_rmpc_bits ctx;
6450 };
6451 
6452 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6453 	u8         status[0x8];
6454 	u8         reserved_0[0x18];
6455 
6456 	u8         syndrome[0x20];
6457 
6458 	u8         reserved_1[0x40];
6459 };
6460 
6461 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6462 	u8         reserved_0[0x14];
6463 	u8         disable_uc_local_lb[0x1];
6464 	u8         disable_mc_local_lb[0x1];
6465 	u8         node_guid[0x1];
6466 	u8         port_guid[0x1];
6467 	u8         min_wqe_inline_mode[0x1];
6468 	u8         mtu[0x1];
6469 	u8         change_event[0x1];
6470 	u8         promisc[0x1];
6471 	u8         permanent_address[0x1];
6472 	u8         addresses_list[0x1];
6473 	u8         roce_en[0x1];
6474 	u8         reserved_1[0x1];
6475 };
6476 
6477 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6478 	u8         opcode[0x10];
6479 	u8         reserved_0[0x10];
6480 
6481 	u8         reserved_1[0x10];
6482 	u8         op_mod[0x10];
6483 
6484 	u8         other_vport[0x1];
6485 	u8         reserved_2[0xf];
6486 	u8         vport_number[0x10];
6487 
6488 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6489 
6490 	u8         reserved_3[0x780];
6491 
6492 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6493 };
6494 
6495 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6496 	u8         status[0x8];
6497 	u8         reserved_0[0x18];
6498 
6499 	u8         syndrome[0x20];
6500 
6501 	u8         reserved_1[0x40];
6502 };
6503 
6504 struct mlx5_ifc_grh_bits {
6505 	u8	ip_version[4];
6506 	u8	traffic_class[8];
6507 	u8	flow_label[20];
6508 	u8	payload_length[16];
6509 	u8	next_header[8];
6510 	u8	hop_limit[8];
6511 	u8	sgid[128];
6512 	u8	dgid[128];
6513 };
6514 
6515 struct mlx5_ifc_bth_bits {
6516 	u8	opcode[8];
6517 	u8	se[1];
6518 	u8	migreq[1];
6519 	u8	pad_count[2];
6520 	u8	tver[4];
6521 	u8	p_key[16];
6522 	u8	reserved8[8];
6523 	u8	dest_qp[24];
6524 	u8	ack_req[1];
6525 	u8	reserved7[7];
6526 	u8	psn[24];
6527 };
6528 
6529 struct mlx5_ifc_aeth_bits {
6530 	u8	syndrome[8];
6531 	u8	msn[24];
6532 };
6533 
6534 struct mlx5_ifc_dceth_bits {
6535 	u8	reserved0[8];
6536 	u8	session_id[24];
6537 	u8	reserved1[8];
6538 	u8	dci_dct[24];
6539 };
6540 
6541 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6542 	u8         opcode[0x10];
6543 	u8         reserved_0[0x10];
6544 
6545 	u8         reserved_1[0x10];
6546 	u8         op_mod[0x10];
6547 
6548 	u8         other_vport[0x1];
6549 	u8         reserved_2[0xb];
6550 	u8         port_num[0x4];
6551 	u8         vport_number[0x10];
6552 
6553 	u8         reserved_3[0x20];
6554 
6555 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6556 };
6557 
6558 enum {
6559         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
6560         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
6561 };
6562 
6563 struct mlx5_ifc_modify_flow_table_out_bits {
6564 	u8         status[0x8];
6565 	u8         reserved_at_8[0x18];
6566 
6567 	u8         syndrome[0x20];
6568 
6569 	u8         reserved_at_40[0x40];
6570 };
6571 
6572 enum {
6573 	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
6574 	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
6575 };
6576 
6577 struct mlx5_ifc_modify_flow_table_in_bits {
6578 	u8         opcode[0x10];
6579 	u8         reserved_at_10[0x10];
6580 
6581 	u8         reserved_at_20[0x10];
6582 	u8         op_mod[0x10];
6583 
6584 	u8         other_vport[0x1];
6585 	u8         reserved_at_41[0xf];
6586 	u8         vport_number[0x10];
6587 
6588 	u8         reserved_at_60[0x10];
6589 	u8         modify_field_select[0x10];
6590 
6591 	u8         table_type[0x8];
6592 	u8         reserved_at_88[0x18];
6593 
6594 	u8         reserved_at_a0[0x8];
6595 	u8         table_id[0x18];
6596 
6597 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6598 };
6599 
6600 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6601 	u8         status[0x8];
6602 	u8         reserved_0[0x18];
6603 
6604 	u8         syndrome[0x20];
6605 
6606 	u8         reserved_1[0x40];
6607 };
6608 
6609 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6610 	u8         reserved[0x1c];
6611 	u8         vport_cvlan_insert[0x1];
6612 	u8         vport_svlan_insert[0x1];
6613 	u8         vport_cvlan_strip[0x1];
6614 	u8         vport_svlan_strip[0x1];
6615 };
6616 
6617 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6618 	u8         opcode[0x10];
6619 	u8         reserved_0[0x10];
6620 
6621 	u8         reserved_1[0x10];
6622 	u8         op_mod[0x10];
6623 
6624 	u8         other_vport[0x1];
6625 	u8         reserved_2[0xf];
6626 	u8         vport_number[0x10];
6627 
6628 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6629 
6630 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6631 };
6632 
6633 struct mlx5_ifc_modify_cq_out_bits {
6634 	u8         status[0x8];
6635 	u8         reserved_0[0x18];
6636 
6637 	u8         syndrome[0x20];
6638 
6639 	u8         reserved_1[0x40];
6640 };
6641 
6642 enum {
6643 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6644 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6645 };
6646 
6647 struct mlx5_ifc_modify_cq_in_bits {
6648 	u8         opcode[0x10];
6649 	u8         uid[0x10];
6650 
6651 	u8         reserved_1[0x10];
6652 	u8         op_mod[0x10];
6653 
6654 	u8         reserved_2[0x8];
6655 	u8         cqn[0x18];
6656 
6657 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6658 
6659 	struct mlx5_ifc_cqc_bits cq_context;
6660 
6661 	u8         reserved_at_280[0x60];
6662 
6663 	u8         cq_umem_valid[0x1];
6664 	u8         reserved_at_2e1[0x1f];
6665 
6666 	u8         reserved_at_300[0x580];
6667 
6668 	u8         pas[0][0x40];
6669 };
6670 
6671 struct mlx5_ifc_modify_cong_status_out_bits {
6672 	u8         status[0x8];
6673 	u8         reserved_0[0x18];
6674 
6675 	u8         syndrome[0x20];
6676 
6677 	u8         reserved_1[0x40];
6678 };
6679 
6680 struct mlx5_ifc_modify_cong_status_in_bits {
6681 	u8         opcode[0x10];
6682 	u8         reserved_0[0x10];
6683 
6684 	u8         reserved_1[0x10];
6685 	u8         op_mod[0x10];
6686 
6687 	u8         reserved_2[0x18];
6688 	u8         priority[0x4];
6689 	u8         cong_protocol[0x4];
6690 
6691 	u8         enable[0x1];
6692 	u8         tag_enable[0x1];
6693 	u8         reserved_3[0x1e];
6694 };
6695 
6696 struct mlx5_ifc_modify_cong_params_out_bits {
6697 	u8         status[0x8];
6698 	u8         reserved_0[0x18];
6699 
6700 	u8         syndrome[0x20];
6701 
6702 	u8         reserved_1[0x40];
6703 };
6704 
6705 struct mlx5_ifc_modify_cong_params_in_bits {
6706 	u8         opcode[0x10];
6707 	u8         reserved_0[0x10];
6708 
6709 	u8         reserved_1[0x10];
6710 	u8         op_mod[0x10];
6711 
6712 	u8         reserved_2[0x1c];
6713 	u8         cong_protocol[0x4];
6714 
6715 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6716 
6717 	u8         reserved_3[0x80];
6718 
6719 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6720 };
6721 
6722 struct mlx5_ifc_manage_pages_out_bits {
6723 	u8         status[0x8];
6724 	u8         reserved_0[0x18];
6725 
6726 	u8         syndrome[0x20];
6727 
6728 	u8         output_num_entries[0x20];
6729 
6730 	u8         reserved_1[0x20];
6731 
6732 	u8         pas[0][0x40];
6733 };
6734 
6735 enum {
6736 	MLX5_PAGES_CANT_GIVE                            = 0x0,
6737 	MLX5_PAGES_GIVE                                 = 0x1,
6738 	MLX5_PAGES_TAKE                                 = 0x2,
6739 };
6740 
6741 struct mlx5_ifc_manage_pages_in_bits {
6742 	u8         opcode[0x10];
6743 	u8         reserved_0[0x10];
6744 
6745 	u8         reserved_1[0x10];
6746 	u8         op_mod[0x10];
6747 
6748 	u8         reserved_2[0x10];
6749 	u8         function_id[0x10];
6750 
6751 	u8         input_num_entries[0x20];
6752 
6753 	u8         pas[0][0x40];
6754 };
6755 
6756 struct mlx5_ifc_mad_ifc_out_bits {
6757 	u8         status[0x8];
6758 	u8         reserved_0[0x18];
6759 
6760 	u8         syndrome[0x20];
6761 
6762 	u8         reserved_1[0x40];
6763 
6764 	u8         response_mad_packet[256][0x8];
6765 };
6766 
6767 struct mlx5_ifc_mad_ifc_in_bits {
6768 	u8         opcode[0x10];
6769 	u8         reserved_0[0x10];
6770 
6771 	u8         reserved_1[0x10];
6772 	u8         op_mod[0x10];
6773 
6774 	u8         remote_lid[0x10];
6775 	u8         reserved_2[0x8];
6776 	u8         port[0x8];
6777 
6778 	u8         reserved_3[0x20];
6779 
6780 	u8         mad[256][0x8];
6781 };
6782 
6783 struct mlx5_ifc_init_hca_out_bits {
6784 	u8         status[0x8];
6785 	u8         reserved_0[0x18];
6786 
6787 	u8         syndrome[0x20];
6788 
6789 	u8         reserved_1[0x40];
6790 };
6791 
6792 enum {
6793 	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
6794 	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
6795 };
6796 
6797 struct mlx5_ifc_init_hca_in_bits {
6798 	u8         opcode[0x10];
6799 	u8         reserved_0[0x10];
6800 
6801 	u8         reserved_1[0x10];
6802 	u8         op_mod[0x10];
6803 
6804 	u8         reserved_2[0x40];
6805 };
6806 
6807 struct mlx5_ifc_init2rtr_qp_out_bits {
6808 	u8         status[0x8];
6809 	u8         reserved_0[0x18];
6810 
6811 	u8         syndrome[0x20];
6812 
6813 	u8         reserved_1[0x40];
6814 };
6815 
6816 struct mlx5_ifc_init2rtr_qp_in_bits {
6817 	u8         opcode[0x10];
6818 	u8         uid[0x10];
6819 
6820 	u8         reserved_1[0x10];
6821 	u8         op_mod[0x10];
6822 
6823 	u8         reserved_2[0x8];
6824 	u8         qpn[0x18];
6825 
6826 	u8         reserved_3[0x20];
6827 
6828 	u8         opt_param_mask[0x20];
6829 
6830 	u8         reserved_4[0x20];
6831 
6832 	struct mlx5_ifc_qpc_bits qpc;
6833 
6834 	u8         reserved_5[0x80];
6835 };
6836 
6837 struct mlx5_ifc_init2init_qp_out_bits {
6838 	u8         status[0x8];
6839 	u8         reserved_0[0x18];
6840 
6841 	u8         syndrome[0x20];
6842 
6843 	u8         reserved_1[0x40];
6844 };
6845 
6846 struct mlx5_ifc_init2init_qp_in_bits {
6847 	u8         opcode[0x10];
6848 	u8         uid[0x10];
6849 
6850 	u8         reserved_1[0x10];
6851 	u8         op_mod[0x10];
6852 
6853 	u8         reserved_2[0x8];
6854 	u8         qpn[0x18];
6855 
6856 	u8         reserved_3[0x20];
6857 
6858 	u8         opt_param_mask[0x20];
6859 
6860 	u8         reserved_4[0x20];
6861 
6862 	struct mlx5_ifc_qpc_bits qpc;
6863 
6864 	u8         reserved_5[0x80];
6865 };
6866 
6867 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6868 	u8         status[0x8];
6869 	u8         reserved_0[0x18];
6870 
6871 	u8         syndrome[0x20];
6872 
6873 	u8         reserved_1[0x40];
6874 
6875 	u8         packet_headers_log[128][0x8];
6876 
6877 	u8         packet_syndrome[64][0x8];
6878 };
6879 
6880 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6881 	u8         opcode[0x10];
6882 	u8         reserved_0[0x10];
6883 
6884 	u8         reserved_1[0x10];
6885 	u8         op_mod[0x10];
6886 
6887 	u8         reserved_2[0x40];
6888 };
6889 
6890 struct mlx5_ifc_encryption_key_obj_bits {
6891 	u8         modify_field_select[0x40];
6892 
6893 	u8         reserved_at_40[0x14];
6894 	u8         key_size[0x4];
6895 	u8         reserved_at_58[0x4];
6896 	u8         key_type[0x4];
6897 
6898 	u8         reserved_at_60[0x8];
6899 	u8         pd[0x18];
6900 
6901 	u8         reserved_at_80[0x180];
6902 
6903 	u8         key[8][0x20];
6904 
6905 	u8         reserved_at_300[0x500];
6906 };
6907 
6908 struct mlx5_ifc_gen_eqe_in_bits {
6909 	u8         opcode[0x10];
6910 	u8         reserved_0[0x10];
6911 
6912 	u8         reserved_1[0x10];
6913 	u8         op_mod[0x10];
6914 
6915 	u8         reserved_2[0x18];
6916 	u8         eq_number[0x8];
6917 
6918 	u8         reserved_3[0x20];
6919 
6920 	u8         eqe[64][0x8];
6921 };
6922 
6923 struct mlx5_ifc_gen_eq_out_bits {
6924 	u8         status[0x8];
6925 	u8         reserved_0[0x18];
6926 
6927 	u8         syndrome[0x20];
6928 
6929 	u8         reserved_1[0x40];
6930 };
6931 
6932 struct mlx5_ifc_enable_hca_out_bits {
6933 	u8         status[0x8];
6934 	u8         reserved_0[0x18];
6935 
6936 	u8         syndrome[0x20];
6937 
6938 	u8         reserved_1[0x20];
6939 };
6940 
6941 struct mlx5_ifc_enable_hca_in_bits {
6942 	u8         opcode[0x10];
6943 	u8         reserved_0[0x10];
6944 
6945 	u8         reserved_1[0x10];
6946 	u8         op_mod[0x10];
6947 
6948 	u8         reserved_2[0x10];
6949 	u8         function_id[0x10];
6950 
6951 	u8         reserved_3[0x20];
6952 };
6953 
6954 struct mlx5_ifc_drain_dct_out_bits {
6955 	u8         status[0x8];
6956 	u8         reserved_0[0x18];
6957 
6958 	u8         syndrome[0x20];
6959 
6960 	u8         reserved_1[0x40];
6961 };
6962 
6963 struct mlx5_ifc_drain_dct_in_bits {
6964 	u8         opcode[0x10];
6965 	u8         uid[0x10];
6966 
6967 	u8         reserved_1[0x10];
6968 	u8         op_mod[0x10];
6969 
6970 	u8         reserved_2[0x8];
6971 	u8         dctn[0x18];
6972 
6973 	u8         reserved_3[0x20];
6974 };
6975 
6976 struct mlx5_ifc_disable_hca_out_bits {
6977 	u8         status[0x8];
6978 	u8         reserved_0[0x18];
6979 
6980 	u8         syndrome[0x20];
6981 
6982 	u8         reserved_1[0x20];
6983 };
6984 
6985 struct mlx5_ifc_disable_hca_in_bits {
6986 	u8         opcode[0x10];
6987 	u8         reserved_0[0x10];
6988 
6989 	u8         reserved_1[0x10];
6990 	u8         op_mod[0x10];
6991 
6992 	u8         reserved_2[0x10];
6993 	u8         function_id[0x10];
6994 
6995 	u8         reserved_3[0x20];
6996 };
6997 
6998 struct mlx5_ifc_detach_from_mcg_out_bits {
6999 	u8         status[0x8];
7000 	u8         reserved_0[0x18];
7001 
7002 	u8         syndrome[0x20];
7003 
7004 	u8         reserved_1[0x40];
7005 };
7006 
7007 struct mlx5_ifc_detach_from_mcg_in_bits {
7008 	u8         opcode[0x10];
7009 	u8         uid[0x10];
7010 
7011 	u8         reserved_1[0x10];
7012 	u8         op_mod[0x10];
7013 
7014 	u8         reserved_2[0x8];
7015 	u8         qpn[0x18];
7016 
7017 	u8         reserved_3[0x20];
7018 
7019 	u8         multicast_gid[16][0x8];
7020 };
7021 
7022 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7023 	u8         status[0x8];
7024 	u8         reserved_0[0x18];
7025 
7026 	u8         syndrome[0x20];
7027 
7028 	u8         reserved_1[0x40];
7029 };
7030 
7031 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7032 	u8         opcode[0x10];
7033 	u8         uid[0x10];
7034 
7035 	u8         reserved_1[0x10];
7036 	u8         op_mod[0x10];
7037 
7038 	u8         reserved_2[0x8];
7039 	u8         xrc_srqn[0x18];
7040 
7041 	u8         reserved_3[0x20];
7042 };
7043 
7044 struct mlx5_ifc_destroy_tis_out_bits {
7045 	u8         status[0x8];
7046 	u8         reserved_0[0x18];
7047 
7048 	u8         syndrome[0x20];
7049 
7050 	u8         reserved_1[0x40];
7051 };
7052 
7053 struct mlx5_ifc_destroy_tis_in_bits {
7054 	u8         opcode[0x10];
7055 	u8         uid[0x10];
7056 
7057 	u8         reserved_1[0x10];
7058 	u8         op_mod[0x10];
7059 
7060 	u8         reserved_2[0x8];
7061 	u8         tisn[0x18];
7062 
7063 	u8         reserved_3[0x20];
7064 };
7065 
7066 struct mlx5_ifc_destroy_tir_out_bits {
7067 	u8         status[0x8];
7068 	u8         reserved_0[0x18];
7069 
7070 	u8         syndrome[0x20];
7071 
7072 	u8         reserved_1[0x40];
7073 };
7074 
7075 struct mlx5_ifc_destroy_tir_in_bits {
7076 	u8         opcode[0x10];
7077 	u8         uid[0x10];
7078 
7079 	u8         reserved_1[0x10];
7080 	u8         op_mod[0x10];
7081 
7082 	u8         reserved_2[0x8];
7083 	u8         tirn[0x18];
7084 
7085 	u8         reserved_3[0x20];
7086 };
7087 
7088 struct mlx5_ifc_destroy_srq_out_bits {
7089 	u8         status[0x8];
7090 	u8         reserved_0[0x18];
7091 
7092 	u8         syndrome[0x20];
7093 
7094 	u8         reserved_1[0x40];
7095 };
7096 
7097 struct mlx5_ifc_destroy_srq_in_bits {
7098 	u8         opcode[0x10];
7099 	u8         uid[0x10];
7100 
7101 	u8         reserved_1[0x10];
7102 	u8         op_mod[0x10];
7103 
7104 	u8         reserved_2[0x8];
7105 	u8         srqn[0x18];
7106 
7107 	u8         reserved_3[0x20];
7108 };
7109 
7110 struct mlx5_ifc_destroy_sq_out_bits {
7111 	u8         status[0x8];
7112 	u8         reserved_0[0x18];
7113 
7114 	u8         syndrome[0x20];
7115 
7116 	u8         reserved_1[0x40];
7117 };
7118 
7119 struct mlx5_ifc_destroy_sq_in_bits {
7120 	u8         opcode[0x10];
7121 	u8         uid[0x10];
7122 
7123 	u8         reserved_1[0x10];
7124 	u8         op_mod[0x10];
7125 
7126 	u8         reserved_2[0x8];
7127 	u8         sqn[0x18];
7128 
7129 	u8         reserved_3[0x20];
7130 };
7131 
7132 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7133 	u8         status[0x8];
7134 	u8         reserved_at_8[0x18];
7135 
7136 	u8         syndrome[0x20];
7137 
7138 	u8         reserved_at_40[0x1c0];
7139 };
7140 
7141 enum {
7142 	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7143 };
7144 
7145 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7146 	u8         opcode[0x10];
7147 	u8         reserved_at_10[0x10];
7148 
7149 	u8         reserved_at_20[0x10];
7150 	u8         op_mod[0x10];
7151 
7152 	u8         scheduling_hierarchy[0x8];
7153 	u8         reserved_at_48[0x18];
7154 
7155 	u8         scheduling_element_id[0x20];
7156 
7157 	u8         reserved_at_80[0x180];
7158 };
7159 
7160 struct mlx5_ifc_destroy_rqt_out_bits {
7161 	u8         status[0x8];
7162 	u8         reserved_0[0x18];
7163 
7164 	u8         syndrome[0x20];
7165 
7166 	u8         reserved_1[0x40];
7167 };
7168 
7169 struct mlx5_ifc_destroy_rqt_in_bits {
7170 	u8         opcode[0x10];
7171 	u8         uid[0x10];
7172 
7173 	u8         reserved_1[0x10];
7174 	u8         op_mod[0x10];
7175 
7176 	u8         reserved_2[0x8];
7177 	u8         rqtn[0x18];
7178 
7179 	u8         reserved_3[0x20];
7180 };
7181 
7182 struct mlx5_ifc_destroy_rq_out_bits {
7183 	u8         status[0x8];
7184 	u8         reserved_0[0x18];
7185 
7186 	u8         syndrome[0x20];
7187 
7188 	u8         reserved_1[0x40];
7189 };
7190 
7191 struct mlx5_ifc_destroy_rq_in_bits {
7192 	u8         opcode[0x10];
7193 	u8         uid[0x10];
7194 
7195 	u8         reserved_1[0x10];
7196 	u8         op_mod[0x10];
7197 
7198 	u8         reserved_2[0x8];
7199 	u8         rqn[0x18];
7200 
7201 	u8         reserved_3[0x20];
7202 };
7203 
7204 struct mlx5_ifc_destroy_rmp_out_bits {
7205 	u8         status[0x8];
7206 	u8         reserved_0[0x18];
7207 
7208 	u8         syndrome[0x20];
7209 
7210 	u8         reserved_1[0x40];
7211 };
7212 
7213 struct mlx5_ifc_destroy_rmp_in_bits {
7214 	u8         opcode[0x10];
7215 	u8         uid[0x10];
7216 
7217 	u8         reserved_1[0x10];
7218 	u8         op_mod[0x10];
7219 
7220 	u8         reserved_2[0x8];
7221 	u8         rmpn[0x18];
7222 
7223 	u8         reserved_3[0x20];
7224 };
7225 
7226 struct mlx5_ifc_destroy_qp_out_bits {
7227 	u8         status[0x8];
7228 	u8         reserved_0[0x18];
7229 
7230 	u8         syndrome[0x20];
7231 
7232 	u8         reserved_1[0x40];
7233 };
7234 
7235 struct mlx5_ifc_destroy_qp_in_bits {
7236 	u8         opcode[0x10];
7237 	u8         uid[0x10];
7238 
7239 	u8         reserved_1[0x10];
7240 	u8         op_mod[0x10];
7241 
7242 	u8         reserved_2[0x8];
7243 	u8         qpn[0x18];
7244 
7245 	u8         reserved_3[0x20];
7246 };
7247 
7248 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
7249 	u8         status[0x8];
7250 	u8         reserved_at_8[0x18];
7251 
7252 	u8         syndrome[0x20];
7253 
7254 	u8         reserved_at_40[0x1c0];
7255 };
7256 
7257 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
7258 	u8         opcode[0x10];
7259 	u8         reserved_at_10[0x10];
7260 
7261 	u8         reserved_at_20[0x10];
7262 	u8         op_mod[0x10];
7263 
7264 	u8         reserved_at_40[0x20];
7265 
7266 	u8         reserved_at_60[0x10];
7267 	u8         qos_para_vport_number[0x10];
7268 
7269 	u8         reserved_at_80[0x180];
7270 };
7271 
7272 struct mlx5_ifc_destroy_psv_out_bits {
7273 	u8         status[0x8];
7274 	u8         reserved_0[0x18];
7275 
7276 	u8         syndrome[0x20];
7277 
7278 	u8         reserved_1[0x40];
7279 };
7280 
7281 struct mlx5_ifc_destroy_psv_in_bits {
7282 	u8         opcode[0x10];
7283 	u8         reserved_0[0x10];
7284 
7285 	u8         reserved_1[0x10];
7286 	u8         op_mod[0x10];
7287 
7288 	u8         reserved_2[0x8];
7289 	u8         psvn[0x18];
7290 
7291 	u8         reserved_3[0x20];
7292 };
7293 
7294 struct mlx5_ifc_destroy_mkey_out_bits {
7295 	u8         status[0x8];
7296 	u8         reserved_0[0x18];
7297 
7298 	u8         syndrome[0x20];
7299 
7300 	u8         reserved_1[0x40];
7301 };
7302 
7303 struct mlx5_ifc_destroy_mkey_in_bits {
7304 	u8         opcode[0x10];
7305 	u8         reserved_0[0x10];
7306 
7307 	u8         reserved_1[0x10];
7308 	u8         op_mod[0x10];
7309 
7310 	u8         reserved_2[0x8];
7311 	u8         mkey_index[0x18];
7312 
7313 	u8         reserved_3[0x20];
7314 };
7315 
7316 struct mlx5_ifc_destroy_flow_table_out_bits {
7317 	u8         status[0x8];
7318 	u8         reserved_0[0x18];
7319 
7320 	u8         syndrome[0x20];
7321 
7322 	u8         reserved_1[0x40];
7323 };
7324 
7325 struct mlx5_ifc_destroy_flow_table_in_bits {
7326 	u8         opcode[0x10];
7327 	u8         reserved_0[0x10];
7328 
7329 	u8         reserved_1[0x10];
7330 	u8         op_mod[0x10];
7331 
7332 	u8         other_vport[0x1];
7333 	u8         reserved_2[0xf];
7334 	u8         vport_number[0x10];
7335 
7336 	u8         reserved_3[0x20];
7337 
7338 	u8         table_type[0x8];
7339 	u8         reserved_4[0x18];
7340 
7341 	u8         reserved_5[0x8];
7342 	u8         table_id[0x18];
7343 
7344 	u8         reserved_6[0x140];
7345 };
7346 
7347 struct mlx5_ifc_destroy_flow_group_out_bits {
7348 	u8         status[0x8];
7349 	u8         reserved_0[0x18];
7350 
7351 	u8         syndrome[0x20];
7352 
7353 	u8         reserved_1[0x40];
7354 };
7355 
7356 struct mlx5_ifc_destroy_flow_group_in_bits {
7357 	u8         opcode[0x10];
7358 	u8         reserved_0[0x10];
7359 
7360 	u8         reserved_1[0x10];
7361 	u8         op_mod[0x10];
7362 
7363 	u8         other_vport[0x1];
7364 	u8         reserved_2[0xf];
7365 	u8         vport_number[0x10];
7366 
7367 	u8         reserved_3[0x20];
7368 
7369 	u8         table_type[0x8];
7370 	u8         reserved_4[0x18];
7371 
7372 	u8         reserved_5[0x8];
7373 	u8         table_id[0x18];
7374 
7375 	u8         group_id[0x20];
7376 
7377 	u8         reserved_6[0x120];
7378 };
7379 
7380 struct mlx5_ifc_destroy_encryption_key_out_bits {
7381 	u8         status[0x8];
7382 	u8         reserved_at_8[0x18];
7383 
7384 	u8         syndrome[0x20];
7385 
7386 	u8         reserved_at_40[0x40];
7387 };
7388 
7389 struct mlx5_ifc_destroy_encryption_key_in_bits {
7390 	u8         opcode[0x10];
7391 	u8         reserved_at_10[0x10];
7392 
7393 	u8         reserved_at_20[0x10];
7394 	u8         obj_type[0x10];
7395 
7396 	u8         obj_id[0x20];
7397 
7398 	u8         reserved_at_60[0x20];
7399 };
7400 
7401 struct mlx5_ifc_destroy_eq_out_bits {
7402 	u8         status[0x8];
7403 	u8         reserved_0[0x18];
7404 
7405 	u8         syndrome[0x20];
7406 
7407 	u8         reserved_1[0x40];
7408 };
7409 
7410 struct mlx5_ifc_destroy_eq_in_bits {
7411 	u8         opcode[0x10];
7412 	u8         reserved_0[0x10];
7413 
7414 	u8         reserved_1[0x10];
7415 	u8         op_mod[0x10];
7416 
7417 	u8         reserved_2[0x18];
7418 	u8         eq_number[0x8];
7419 
7420 	u8         reserved_3[0x20];
7421 };
7422 
7423 struct mlx5_ifc_destroy_dct_out_bits {
7424 	u8         status[0x8];
7425 	u8         reserved_0[0x18];
7426 
7427 	u8         syndrome[0x20];
7428 
7429 	u8         reserved_1[0x40];
7430 };
7431 
7432 struct mlx5_ifc_destroy_dct_in_bits {
7433 	u8         opcode[0x10];
7434 	u8         uid[0x10];
7435 
7436 	u8         reserved_1[0x10];
7437 	u8         op_mod[0x10];
7438 
7439 	u8         reserved_2[0x8];
7440 	u8         dctn[0x18];
7441 
7442 	u8         reserved_3[0x20];
7443 };
7444 
7445 struct mlx5_ifc_destroy_cq_out_bits {
7446 	u8         status[0x8];
7447 	u8         reserved_0[0x18];
7448 
7449 	u8         syndrome[0x20];
7450 
7451 	u8         reserved_1[0x40];
7452 };
7453 
7454 struct mlx5_ifc_destroy_cq_in_bits {
7455 	u8         opcode[0x10];
7456 	u8         uid[0x10];
7457 
7458 	u8         reserved_1[0x10];
7459 	u8         op_mod[0x10];
7460 
7461 	u8         reserved_2[0x8];
7462 	u8         cqn[0x18];
7463 
7464 	u8         reserved_3[0x20];
7465 };
7466 
7467 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7468 	u8         status[0x8];
7469 	u8         reserved_0[0x18];
7470 
7471 	u8         syndrome[0x20];
7472 
7473 	u8         reserved_1[0x40];
7474 };
7475 
7476 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7477 	u8         opcode[0x10];
7478 	u8         reserved_0[0x10];
7479 
7480 	u8         reserved_1[0x10];
7481 	u8         op_mod[0x10];
7482 
7483 	u8         reserved_2[0x20];
7484 
7485 	u8         reserved_3[0x10];
7486 	u8         vxlan_udp_port[0x10];
7487 };
7488 
7489 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7490 	u8         status[0x8];
7491 	u8         reserved_0[0x18];
7492 
7493 	u8         syndrome[0x20];
7494 
7495 	u8         reserved_1[0x40];
7496 };
7497 
7498 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7499 	u8         opcode[0x10];
7500 	u8         reserved_0[0x10];
7501 
7502 	u8         reserved_1[0x10];
7503 	u8         op_mod[0x10];
7504 
7505 	u8         reserved_2[0x60];
7506 
7507 	u8         reserved_3[0x8];
7508 	u8         table_index[0x18];
7509 
7510 	u8         reserved_4[0x140];
7511 };
7512 
7513 struct mlx5_ifc_delete_fte_out_bits {
7514 	u8         status[0x8];
7515 	u8         reserved_0[0x18];
7516 
7517 	u8         syndrome[0x20];
7518 
7519 	u8         reserved_1[0x40];
7520 };
7521 
7522 struct mlx5_ifc_delete_fte_in_bits {
7523 	u8         opcode[0x10];
7524 	u8         reserved_0[0x10];
7525 
7526 	u8         reserved_1[0x10];
7527 	u8         op_mod[0x10];
7528 
7529 	u8         other_vport[0x1];
7530 	u8         reserved_2[0xf];
7531 	u8         vport_number[0x10];
7532 
7533 	u8         reserved_3[0x20];
7534 
7535 	u8         table_type[0x8];
7536 	u8         reserved_4[0x18];
7537 
7538 	u8         reserved_5[0x8];
7539 	u8         table_id[0x18];
7540 
7541 	u8         reserved_6[0x40];
7542 
7543 	u8         flow_index[0x20];
7544 
7545 	u8         reserved_7[0xe0];
7546 };
7547 
7548 struct mlx5_ifc_dealloc_xrcd_out_bits {
7549 	u8         status[0x8];
7550 	u8         reserved_0[0x18];
7551 
7552 	u8         syndrome[0x20];
7553 
7554 	u8         reserved_1[0x40];
7555 };
7556 
7557 struct mlx5_ifc_dealloc_xrcd_in_bits {
7558 	u8         opcode[0x10];
7559 	u8         uid[0x10];
7560 
7561 	u8         reserved_1[0x10];
7562 	u8         op_mod[0x10];
7563 
7564 	u8         reserved_2[0x8];
7565 	u8         xrcd[0x18];
7566 
7567 	u8         reserved_3[0x20];
7568 };
7569 
7570 struct mlx5_ifc_dealloc_uar_out_bits {
7571 	u8         status[0x8];
7572 	u8         reserved_0[0x18];
7573 
7574 	u8         syndrome[0x20];
7575 
7576 	u8         reserved_1[0x40];
7577 };
7578 
7579 struct mlx5_ifc_dealloc_uar_in_bits {
7580 	u8         opcode[0x10];
7581 	u8         uid[0x10];
7582 
7583 	u8         reserved_1[0x10];
7584 	u8         op_mod[0x10];
7585 
7586 	u8         reserved_2[0x8];
7587 	u8         uar[0x18];
7588 
7589 	u8         reserved_3[0x20];
7590 };
7591 
7592 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7593 	u8         status[0x8];
7594 	u8         reserved_0[0x18];
7595 
7596 	u8         syndrome[0x20];
7597 
7598 	u8         reserved_1[0x40];
7599 };
7600 
7601 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7602 	u8         opcode[0x10];
7603 	u8         uid[0x10];
7604 
7605 	u8         reserved_1[0x10];
7606 	u8         op_mod[0x10];
7607 
7608 	u8         reserved_2[0x8];
7609 	u8         transport_domain[0x18];
7610 
7611 	u8         reserved_3[0x20];
7612 };
7613 
7614 struct mlx5_ifc_dealloc_q_counter_out_bits {
7615 	u8         status[0x8];
7616 	u8         reserved_0[0x18];
7617 
7618 	u8         syndrome[0x20];
7619 
7620 	u8         reserved_1[0x40];
7621 };
7622 
7623 struct mlx5_ifc_counter_id_bits {
7624 	u8         reserved[0x10];
7625 	u8         counter_id[0x10];
7626 };
7627 
7628 struct mlx5_ifc_diagnostic_params_context_bits {
7629 	u8         num_of_counters[0x10];
7630 	u8         reserved_2[0x8];
7631 	u8         log_num_of_samples[0x8];
7632 
7633 	u8         single[0x1];
7634 	u8         repetitive[0x1];
7635 	u8         sync[0x1];
7636 	u8         clear[0x1];
7637 	u8         on_demand[0x1];
7638 	u8         enable[0x1];
7639 	u8         reserved_3[0x12];
7640 	u8         log_sample_period[0x8];
7641 
7642 	u8         reserved_4[0x80];
7643 
7644 	struct mlx5_ifc_counter_id_bits counter_id[0];
7645 };
7646 
7647 struct mlx5_ifc_query_diagnostic_params_in_bits {
7648 	u8         opcode[0x10];
7649 	u8         reserved_at_10[0x10];
7650 
7651 	u8         reserved_at_20[0x10];
7652 	u8         op_mod[0x10];
7653 
7654 	u8         reserved_at_40[0x40];
7655 };
7656 
7657 struct mlx5_ifc_query_diagnostic_params_out_bits {
7658 	u8         status[0x8];
7659 	u8         reserved_at_8[0x18];
7660 
7661 	u8         syndrome[0x20];
7662 
7663 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7664 };
7665 
7666 struct mlx5_ifc_set_diagnostic_params_in_bits {
7667 	u8         opcode[0x10];
7668 	u8         reserved_0[0x10];
7669 
7670 	u8         reserved_1[0x10];
7671 	u8         op_mod[0x10];
7672 
7673 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7674 };
7675 
7676 struct mlx5_ifc_set_diagnostic_params_out_bits {
7677 	u8         status[0x8];
7678 	u8         reserved_0[0x18];
7679 
7680 	u8         syndrome[0x20];
7681 
7682 	u8         reserved_1[0x40];
7683 };
7684 
7685 struct mlx5_ifc_query_diagnostic_counters_in_bits {
7686 	u8         opcode[0x10];
7687 	u8         reserved_0[0x10];
7688 
7689 	u8         reserved_1[0x10];
7690 	u8         op_mod[0x10];
7691 
7692 	u8         num_of_samples[0x10];
7693 	u8         sample_index[0x10];
7694 
7695 	u8         reserved_2[0x20];
7696 };
7697 
7698 struct mlx5_ifc_diagnostic_counter_bits {
7699 	u8         counter_id[0x10];
7700 	u8         sample_id[0x10];
7701 
7702 	u8         time_stamp_31_0[0x20];
7703 
7704 	u8         counter_value_h[0x20];
7705 
7706 	u8         counter_value_l[0x20];
7707 };
7708 
7709 struct mlx5_ifc_query_diagnostic_counters_out_bits {
7710 	u8         status[0x8];
7711 	u8         reserved_0[0x18];
7712 
7713 	u8         syndrome[0x20];
7714 
7715 	u8         reserved_1[0x40];
7716 
7717 	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
7718 };
7719 
7720 struct mlx5_ifc_dealloc_q_counter_in_bits {
7721 	u8         opcode[0x10];
7722 	u8         reserved_0[0x10];
7723 
7724 	u8         reserved_1[0x10];
7725 	u8         op_mod[0x10];
7726 
7727 	u8         reserved_2[0x18];
7728 	u8         counter_set_id[0x8];
7729 
7730 	u8         reserved_3[0x20];
7731 };
7732 
7733 struct mlx5_ifc_dealloc_pd_out_bits {
7734 	u8         status[0x8];
7735 	u8         reserved_0[0x18];
7736 
7737 	u8         syndrome[0x20];
7738 
7739 	u8         reserved_1[0x40];
7740 };
7741 
7742 struct mlx5_ifc_dealloc_pd_in_bits {
7743 	u8         opcode[0x10];
7744 	u8         uid[0x10];
7745 
7746 	u8         reserved_1[0x10];
7747 	u8         op_mod[0x10];
7748 
7749 	u8         reserved_2[0x8];
7750 	u8         pd[0x18];
7751 
7752 	u8         reserved_3[0x20];
7753 };
7754 
7755 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7756 	u8         status[0x8];
7757 	u8         reserved_0[0x18];
7758 
7759 	u8         syndrome[0x20];
7760 
7761 	u8         reserved_1[0x40];
7762 };
7763 
7764 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7765 	u8         opcode[0x10];
7766 	u8         reserved_0[0x10];
7767 
7768 	u8         reserved_1[0x10];
7769 	u8         op_mod[0x10];
7770 
7771 	u8         flow_counter_id[0x20];
7772 
7773 	u8         reserved_3[0x20];
7774 };
7775 
7776 struct mlx5_ifc_create_xrq_out_bits {
7777 	u8         status[0x8];
7778 	u8         reserved_at_8[0x18];
7779 
7780 	u8         syndrome[0x20];
7781 
7782 	u8         reserved_at_40[0x8];
7783 	u8         xrqn[0x18];
7784 
7785 	u8         reserved_at_60[0x20];
7786 };
7787 
7788 struct mlx5_ifc_create_xrq_in_bits {
7789 	u8         opcode[0x10];
7790 	u8         uid[0x10];
7791 
7792 	u8         reserved_at_20[0x10];
7793 	u8         op_mod[0x10];
7794 
7795 	u8         reserved_at_40[0x40];
7796 
7797 	struct mlx5_ifc_xrqc_bits xrq_context;
7798 };
7799 
7800 struct mlx5_ifc_deactivate_tracer_out_bits {
7801 	u8         status[0x8];
7802 	u8         reserved_0[0x18];
7803 
7804 	u8         syndrome[0x20];
7805 
7806 	u8         reserved_1[0x40];
7807 };
7808 
7809 struct mlx5_ifc_deactivate_tracer_in_bits {
7810 	u8         opcode[0x10];
7811 	u8         reserved_0[0x10];
7812 
7813 	u8         reserved_1[0x10];
7814 	u8         op_mod[0x10];
7815 
7816 	u8         mkey[0x20];
7817 
7818 	u8         reserved_2[0x20];
7819 };
7820 
7821 struct mlx5_ifc_create_xrc_srq_out_bits {
7822 	u8         status[0x8];
7823 	u8         reserved_0[0x18];
7824 
7825 	u8         syndrome[0x20];
7826 
7827 	u8         reserved_1[0x8];
7828 	u8         xrc_srqn[0x18];
7829 
7830 	u8         reserved_2[0x20];
7831 };
7832 
7833 struct mlx5_ifc_create_xrc_srq_in_bits {
7834 	u8         opcode[0x10];
7835 	u8         uid[0x10];
7836 
7837 	u8         reserved_1[0x10];
7838 	u8         op_mod[0x10];
7839 
7840 	u8         reserved_2[0x40];
7841 
7842 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7843 
7844 	u8         reserved_at_280[0x60];
7845 
7846 	u8         xrc_srq_umem_valid[0x1];
7847 	u8         reserved_at_2e1[0x1f];
7848 
7849 	u8         reserved_at_300[0x580];
7850 
7851 	u8         pas[0][0x40];
7852 };
7853 
7854 struct mlx5_ifc_create_tis_out_bits {
7855 	u8         status[0x8];
7856 	u8         reserved_0[0x18];
7857 
7858 	u8         syndrome[0x20];
7859 
7860 	u8         reserved_1[0x8];
7861 	u8         tisn[0x18];
7862 
7863 	u8         reserved_2[0x20];
7864 };
7865 
7866 struct mlx5_ifc_create_tis_in_bits {
7867 	u8         opcode[0x10];
7868 	u8         uid[0x10];
7869 
7870 	u8         reserved_1[0x10];
7871 	u8         op_mod[0x10];
7872 
7873 	u8         reserved_2[0xc0];
7874 
7875 	struct mlx5_ifc_tisc_bits ctx;
7876 };
7877 
7878 struct mlx5_ifc_create_tir_out_bits {
7879 	u8         status[0x8];
7880 	u8         reserved_0[0x18];
7881 
7882 	u8         syndrome[0x20];
7883 
7884 	u8         reserved_1[0x8];
7885 	u8         tirn[0x18];
7886 
7887 	u8         reserved_2[0x20];
7888 };
7889 
7890 struct mlx5_ifc_create_tir_in_bits {
7891 	u8         opcode[0x10];
7892 	u8         uid[0x10];
7893 
7894 	u8         reserved_1[0x10];
7895 	u8         op_mod[0x10];
7896 
7897 	u8         reserved_2[0xc0];
7898 
7899 	struct mlx5_ifc_tirc_bits tir_context;
7900 };
7901 
7902 struct mlx5_ifc_create_srq_out_bits {
7903 	u8         status[0x8];
7904 	u8         reserved_0[0x18];
7905 
7906 	u8         syndrome[0x20];
7907 
7908 	u8         reserved_1[0x8];
7909 	u8         srqn[0x18];
7910 
7911 	u8         reserved_2[0x20];
7912 };
7913 
7914 struct mlx5_ifc_create_srq_in_bits {
7915 	u8         opcode[0x10];
7916 	u8         uid[0x10];
7917 
7918 	u8         reserved_1[0x10];
7919 	u8         op_mod[0x10];
7920 
7921 	u8         reserved_2[0x40];
7922 
7923 	struct mlx5_ifc_srqc_bits srq_context_entry;
7924 
7925 	u8         reserved_3[0x600];
7926 
7927 	u8         pas[0][0x40];
7928 };
7929 
7930 struct mlx5_ifc_create_sq_out_bits {
7931 	u8         status[0x8];
7932 	u8         reserved_0[0x18];
7933 
7934 	u8         syndrome[0x20];
7935 
7936 	u8         reserved_1[0x8];
7937 	u8         sqn[0x18];
7938 
7939 	u8         reserved_2[0x20];
7940 };
7941 
7942 struct mlx5_ifc_create_sq_in_bits {
7943 	u8         opcode[0x10];
7944 	u8         uid[0x10];
7945 
7946 	u8         reserved_1[0x10];
7947 	u8         op_mod[0x10];
7948 
7949 	u8         reserved_2[0xc0];
7950 
7951 	struct mlx5_ifc_sqc_bits ctx;
7952 };
7953 
7954 struct mlx5_ifc_create_scheduling_element_out_bits {
7955 	u8         status[0x8];
7956 	u8         reserved_at_8[0x18];
7957 
7958 	u8         syndrome[0x20];
7959 
7960 	u8         reserved_at_40[0x40];
7961 
7962 	u8         scheduling_element_id[0x20];
7963 
7964 	u8         reserved_at_a0[0x160];
7965 };
7966 
7967 enum {
7968 	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7969 };
7970 
7971 struct mlx5_ifc_create_scheduling_element_in_bits {
7972 	u8         opcode[0x10];
7973 	u8         reserved_at_10[0x10];
7974 
7975 	u8         reserved_at_20[0x10];
7976 	u8         op_mod[0x10];
7977 
7978 	u8         scheduling_hierarchy[0x8];
7979 	u8         reserved_at_48[0x18];
7980 
7981 	u8         reserved_at_60[0xa0];
7982 
7983 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7984 
7985 	u8         reserved_at_300[0x100];
7986 };
7987 
7988 struct mlx5_ifc_create_rqt_out_bits {
7989 	u8         status[0x8];
7990 	u8         reserved_0[0x18];
7991 
7992 	u8         syndrome[0x20];
7993 
7994 	u8         reserved_1[0x8];
7995 	u8         rqtn[0x18];
7996 
7997 	u8         reserved_2[0x20];
7998 };
7999 
8000 struct mlx5_ifc_create_rqt_in_bits {
8001 	u8         opcode[0x10];
8002 	u8         uid[0x10];
8003 
8004 	u8         reserved_1[0x10];
8005 	u8         op_mod[0x10];
8006 
8007 	u8         reserved_2[0xc0];
8008 
8009 	struct mlx5_ifc_rqtc_bits rqt_context;
8010 };
8011 
8012 struct mlx5_ifc_create_rq_out_bits {
8013 	u8         status[0x8];
8014 	u8         reserved_0[0x18];
8015 
8016 	u8         syndrome[0x20];
8017 
8018 	u8         reserved_1[0x8];
8019 	u8         rqn[0x18];
8020 
8021 	u8         reserved_2[0x20];
8022 };
8023 
8024 struct mlx5_ifc_create_rq_in_bits {
8025 	u8         opcode[0x10];
8026 	u8         uid[0x10];
8027 
8028 	u8         reserved_1[0x10];
8029 	u8         op_mod[0x10];
8030 
8031 	u8         reserved_2[0xc0];
8032 
8033 	struct mlx5_ifc_rqc_bits ctx;
8034 };
8035 
8036 struct mlx5_ifc_create_rmp_out_bits {
8037 	u8         status[0x8];
8038 	u8         reserved_0[0x18];
8039 
8040 	u8         syndrome[0x20];
8041 
8042 	u8         reserved_1[0x8];
8043 	u8         rmpn[0x18];
8044 
8045 	u8         reserved_2[0x20];
8046 };
8047 
8048 struct mlx5_ifc_create_rmp_in_bits {
8049 	u8         opcode[0x10];
8050 	u8         uid[0x10];
8051 
8052 	u8         reserved_1[0x10];
8053 	u8         op_mod[0x10];
8054 
8055 	u8         reserved_2[0xc0];
8056 
8057 	struct mlx5_ifc_rmpc_bits ctx;
8058 };
8059 
8060 struct mlx5_ifc_create_qp_out_bits {
8061 	u8         status[0x8];
8062 	u8         reserved_0[0x18];
8063 
8064 	u8         syndrome[0x20];
8065 
8066 	u8         reserved_1[0x8];
8067 	u8         qpn[0x18];
8068 
8069 	u8         reserved_2[0x20];
8070 };
8071 
8072 struct mlx5_ifc_create_qp_in_bits {
8073 	u8         opcode[0x10];
8074 	u8         uid[0x10];
8075 
8076 	u8         reserved_1[0x10];
8077 	u8         op_mod[0x10];
8078 
8079 	u8         reserved_2[0x8];
8080 	u8         input_qpn[0x18];
8081 
8082 	u8         reserved_3[0x20];
8083 
8084 	u8         opt_param_mask[0x20];
8085 
8086 	u8         reserved_4[0x20];
8087 
8088 	struct mlx5_ifc_qpc_bits qpc;
8089 
8090 	u8         reserved_at_800[0x60];
8091 
8092 	u8         wq_umem_valid[0x1];
8093 	u8         reserved_at_861[0x1f];
8094 
8095 	u8         pas[0][0x40];
8096 };
8097 
8098 struct mlx5_ifc_create_qos_para_vport_out_bits {
8099 	u8         status[0x8];
8100 	u8         reserved_at_8[0x18];
8101 
8102 	u8         syndrome[0x20];
8103 
8104 	u8         reserved_at_40[0x20];
8105 
8106 	u8         reserved_at_60[0x10];
8107 	u8         qos_para_vport_number[0x10];
8108 
8109 	u8         reserved_at_80[0x180];
8110 };
8111 
8112 struct mlx5_ifc_create_qos_para_vport_in_bits {
8113 	u8         opcode[0x10];
8114 	u8         reserved_at_10[0x10];
8115 
8116 	u8         reserved_at_20[0x10];
8117 	u8         op_mod[0x10];
8118 
8119 	u8         reserved_at_40[0x1c0];
8120 };
8121 
8122 struct mlx5_ifc_create_psv_out_bits {
8123 	u8         status[0x8];
8124 	u8         reserved_0[0x18];
8125 
8126 	u8         syndrome[0x20];
8127 
8128 	u8         reserved_1[0x40];
8129 
8130 	u8         reserved_2[0x8];
8131 	u8         psv0_index[0x18];
8132 
8133 	u8         reserved_3[0x8];
8134 	u8         psv1_index[0x18];
8135 
8136 	u8         reserved_4[0x8];
8137 	u8         psv2_index[0x18];
8138 
8139 	u8         reserved_5[0x8];
8140 	u8         psv3_index[0x18];
8141 };
8142 
8143 struct mlx5_ifc_create_psv_in_bits {
8144 	u8         opcode[0x10];
8145 	u8         reserved_0[0x10];
8146 
8147 	u8         reserved_1[0x10];
8148 	u8         op_mod[0x10];
8149 
8150 	u8         num_psv[0x4];
8151 	u8         reserved_2[0x4];
8152 	u8         pd[0x18];
8153 
8154 	u8         reserved_3[0x20];
8155 };
8156 
8157 struct mlx5_ifc_create_mkey_out_bits {
8158 	u8         status[0x8];
8159 	u8         reserved_0[0x18];
8160 
8161 	u8         syndrome[0x20];
8162 
8163 	u8         reserved_1[0x8];
8164 	u8         mkey_index[0x18];
8165 
8166 	u8         reserved_2[0x20];
8167 };
8168 
8169 struct mlx5_ifc_create_mkey_in_bits {
8170 	u8         opcode[0x10];
8171 	u8         reserved_0[0x10];
8172 
8173 	u8         reserved_1[0x10];
8174 	u8         op_mod[0x10];
8175 
8176 	u8         reserved_2[0x20];
8177 
8178 	u8         pg_access[0x1];
8179 	u8         mkey_umem_valid[0x1];
8180 	u8         reserved_at_62[0x1e];
8181 
8182 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8183 
8184 	u8         reserved_4[0x80];
8185 
8186 	u8         translations_octword_actual_size[0x20];
8187 
8188 	u8         reserved_5[0x560];
8189 
8190 	u8         klm_pas_mtt[0][0x20];
8191 };
8192 
8193 struct mlx5_ifc_create_flow_table_out_bits {
8194 	u8         status[0x8];
8195 	u8         reserved_0[0x18];
8196 
8197 	u8         syndrome[0x20];
8198 
8199 	u8         reserved_1[0x8];
8200 	u8         table_id[0x18];
8201 
8202 	u8         reserved_2[0x20];
8203 };
8204 
8205 struct mlx5_ifc_create_flow_table_in_bits {
8206         u8         opcode[0x10];
8207         u8         uid[0x10];
8208 
8209         u8         reserved_at_20[0x10];
8210         u8         op_mod[0x10];
8211 
8212         u8         other_vport[0x1];
8213         u8         reserved_at_41[0xf];
8214         u8         vport_number[0x10];
8215 
8216         u8         reserved_at_60[0x20];
8217 
8218         u8         table_type[0x8];
8219         u8         reserved_at_88[0x18];
8220 
8221         u8         reserved_at_a0[0x20];
8222 
8223         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8224 };
8225 
8226 struct mlx5_ifc_create_flow_group_out_bits {
8227 	u8         status[0x8];
8228 	u8         reserved_0[0x18];
8229 
8230 	u8         syndrome[0x20];
8231 
8232 	u8         reserved_1[0x8];
8233 	u8         group_id[0x18];
8234 
8235 	u8         reserved_2[0x20];
8236 };
8237 
8238 enum {
8239 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8240 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8241 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8242 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8243 };
8244 
8245 struct mlx5_ifc_create_flow_group_in_bits {
8246         u8         opcode[0x10];
8247         u8         reserved_at_10[0x10];
8248 
8249         u8         reserved_at_20[0x10];
8250         u8         op_mod[0x10];
8251 
8252         u8         other_vport[0x1];
8253         u8         reserved_at_41[0xf];
8254         u8         vport_number[0x10];
8255 
8256         u8         reserved_at_60[0x20];
8257 
8258         u8         table_type[0x8];
8259         u8         reserved_at_88[0x4];
8260         u8         group_type[0x4];
8261         u8         reserved_at_90[0x10];
8262 
8263         u8         reserved_at_a0[0x8];
8264         u8         table_id[0x18];
8265 
8266         u8         source_eswitch_owner_vhca_id_valid[0x1];
8267 
8268         u8         reserved_at_c1[0x1f];
8269 
8270         u8         start_flow_index[0x20];
8271 
8272         u8         reserved_at_100[0x20];
8273 
8274         u8         end_flow_index[0x20];
8275 
8276         u8         reserved_at_140[0x10];
8277         u8         match_definer_id[0x10];
8278 
8279         u8         reserved_at_160[0x80];
8280 
8281         u8         reserved_at_1e0[0x18];
8282         u8         match_criteria_enable[0x8];
8283 
8284         struct mlx5_ifc_fte_match_param_bits match_criteria;
8285 
8286         u8         reserved_at_1200[0xe00];
8287 };
8288 
8289 struct mlx5_ifc_create_encryption_key_out_bits {
8290 	u8         status[0x8];
8291 	u8         reserved_at_8[0x18];
8292 
8293 	u8         syndrome[0x20];
8294 
8295 	u8         obj_id[0x20];
8296 
8297 	u8         reserved_at_60[0x20];
8298 };
8299 
8300 struct mlx5_ifc_create_encryption_key_in_bits {
8301 	u8         opcode[0x10];
8302 	u8         reserved_at_10[0x10];
8303 
8304 	u8         reserved_at_20[0x10];
8305 	u8         obj_type[0x10];
8306 
8307 	u8         reserved_at_40[0x40];
8308 
8309 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
8310 };
8311 
8312 struct mlx5_ifc_create_eq_out_bits {
8313 	u8         status[0x8];
8314 	u8         reserved_0[0x18];
8315 
8316 	u8         syndrome[0x20];
8317 
8318 	u8         reserved_1[0x18];
8319 	u8         eq_number[0x8];
8320 
8321 	u8         reserved_2[0x20];
8322 };
8323 
8324 struct mlx5_ifc_create_eq_in_bits {
8325 	u8         opcode[0x10];
8326 	u8         uid[0x10];
8327 
8328 	u8         reserved_1[0x10];
8329 	u8         op_mod[0x10];
8330 
8331 	u8         reserved_2[0x40];
8332 
8333 	struct mlx5_ifc_eqc_bits eq_context_entry;
8334 
8335 	u8         reserved_3[0x40];
8336 
8337 	u8         event_bitmask[0x40];
8338 
8339 	u8         reserved_4[0x580];
8340 
8341 	u8         pas[0][0x40];
8342 };
8343 
8344 struct mlx5_ifc_create_dct_out_bits {
8345 	u8         status[0x8];
8346 	u8         reserved_0[0x18];
8347 
8348 	u8         syndrome[0x20];
8349 
8350 	u8         reserved_1[0x8];
8351 	u8         dctn[0x18];
8352 
8353 	u8         reserved_2[0x20];
8354 };
8355 
8356 struct mlx5_ifc_create_dct_in_bits {
8357 	u8         opcode[0x10];
8358 	u8         uid[0x10];
8359 
8360 	u8         reserved_1[0x10];
8361 	u8         op_mod[0x10];
8362 
8363 	u8         reserved_2[0x40];
8364 
8365 	struct mlx5_ifc_dctc_bits dct_context_entry;
8366 
8367 	u8         reserved_3[0x180];
8368 };
8369 
8370 struct mlx5_ifc_create_cq_out_bits {
8371 	u8         status[0x8];
8372 	u8         reserved_0[0x18];
8373 
8374 	u8         syndrome[0x20];
8375 
8376 	u8         reserved_1[0x8];
8377 	u8         cqn[0x18];
8378 
8379 	u8         reserved_2[0x20];
8380 };
8381 
8382 struct mlx5_ifc_create_cq_in_bits {
8383 	u8         opcode[0x10];
8384 	u8         uid[0x10];
8385 
8386 	u8         reserved_1[0x10];
8387 	u8         op_mod[0x10];
8388 
8389 	u8         reserved_2[0x40];
8390 
8391 	struct mlx5_ifc_cqc_bits cq_context;
8392 
8393 	u8         reserved_at_280[0x60];
8394 
8395 	u8         cq_umem_valid[0x1];
8396 	u8         reserved_at_2e1[0x59f];
8397 
8398 	u8         pas[0][0x40];
8399 };
8400 
8401 struct mlx5_ifc_config_int_moderation_out_bits {
8402 	u8         status[0x8];
8403 	u8         reserved_0[0x18];
8404 
8405 	u8         syndrome[0x20];
8406 
8407 	u8         reserved_1[0x4];
8408 	u8         min_delay[0xc];
8409 	u8         int_vector[0x10];
8410 
8411 	u8         reserved_2[0x20];
8412 };
8413 
8414 enum {
8415 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8416 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8417 };
8418 
8419 struct mlx5_ifc_config_int_moderation_in_bits {
8420 	u8         opcode[0x10];
8421 	u8         reserved_0[0x10];
8422 
8423 	u8         reserved_1[0x10];
8424 	u8         op_mod[0x10];
8425 
8426 	u8         reserved_2[0x4];
8427 	u8         min_delay[0xc];
8428 	u8         int_vector[0x10];
8429 
8430 	u8         reserved_3[0x20];
8431 };
8432 
8433 struct mlx5_ifc_attach_to_mcg_out_bits {
8434 	u8         status[0x8];
8435 	u8         reserved_0[0x18];
8436 
8437 	u8         syndrome[0x20];
8438 
8439 	u8         reserved_1[0x40];
8440 };
8441 
8442 struct mlx5_ifc_attach_to_mcg_in_bits {
8443 	u8         opcode[0x10];
8444 	u8         uid[0x10];
8445 
8446 	u8         reserved_1[0x10];
8447 	u8         op_mod[0x10];
8448 
8449 	u8         reserved_2[0x8];
8450 	u8         qpn[0x18];
8451 
8452 	u8         reserved_3[0x20];
8453 
8454 	u8         multicast_gid[16][0x8];
8455 };
8456 
8457 struct mlx5_ifc_arm_xrq_out_bits {
8458 	u8         status[0x8];
8459 	u8         reserved_at_8[0x18];
8460 
8461 	u8         syndrome[0x20];
8462 
8463 	u8         reserved_at_40[0x40];
8464 };
8465 
8466 struct mlx5_ifc_arm_xrq_in_bits {
8467 	u8         opcode[0x10];
8468 	u8         reserved_at_10[0x10];
8469 
8470 	u8         reserved_at_20[0x10];
8471 	u8         op_mod[0x10];
8472 
8473 	u8         reserved_at_40[0x8];
8474 	u8         xrqn[0x18];
8475 
8476 	u8         reserved_at_60[0x10];
8477 	u8         lwm[0x10];
8478 };
8479 
8480 struct mlx5_ifc_arm_xrc_srq_out_bits {
8481 	u8         status[0x8];
8482 	u8         reserved_0[0x18];
8483 
8484 	u8         syndrome[0x20];
8485 
8486 	u8         reserved_1[0x40];
8487 };
8488 
8489 enum {
8490 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8491 };
8492 
8493 struct mlx5_ifc_arm_xrc_srq_in_bits {
8494 	u8         opcode[0x10];
8495 	u8         uid[0x10];
8496 
8497 	u8         reserved_1[0x10];
8498 	u8         op_mod[0x10];
8499 
8500 	u8         reserved_2[0x8];
8501 	u8         xrc_srqn[0x18];
8502 
8503 	u8         reserved_3[0x10];
8504 	u8         lwm[0x10];
8505 };
8506 
8507 struct mlx5_ifc_arm_rq_out_bits {
8508 	u8         status[0x8];
8509 	u8         reserved_0[0x18];
8510 
8511 	u8         syndrome[0x20];
8512 
8513 	u8         reserved_1[0x40];
8514 };
8515 
8516 enum {
8517 	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
8518 };
8519 
8520 struct mlx5_ifc_arm_rq_in_bits {
8521 	u8         opcode[0x10];
8522 	u8         uid[0x10];
8523 
8524 	u8         reserved_1[0x10];
8525 	u8         op_mod[0x10];
8526 
8527 	u8         reserved_2[0x8];
8528 	u8         srq_number[0x18];
8529 
8530 	u8         reserved_3[0x10];
8531 	u8         lwm[0x10];
8532 };
8533 
8534 struct mlx5_ifc_arm_dct_out_bits {
8535 	u8         status[0x8];
8536 	u8         reserved_0[0x18];
8537 
8538 	u8         syndrome[0x20];
8539 
8540 	u8         reserved_1[0x40];
8541 };
8542 
8543 struct mlx5_ifc_arm_dct_in_bits {
8544 	u8         opcode[0x10];
8545 	u8         reserved_0[0x10];
8546 
8547 	u8         reserved_1[0x10];
8548 	u8         op_mod[0x10];
8549 
8550 	u8         reserved_2[0x8];
8551 	u8         dctn[0x18];
8552 
8553 	u8         reserved_3[0x20];
8554 };
8555 
8556 struct mlx5_ifc_alloc_xrcd_out_bits {
8557 	u8         status[0x8];
8558 	u8         reserved_0[0x18];
8559 
8560 	u8         syndrome[0x20];
8561 
8562 	u8         reserved_1[0x8];
8563 	u8         xrcd[0x18];
8564 
8565 	u8         reserved_2[0x20];
8566 };
8567 
8568 struct mlx5_ifc_alloc_xrcd_in_bits {
8569 	u8         opcode[0x10];
8570 	u8         uid[0x10];
8571 
8572 	u8         reserved_1[0x10];
8573 	u8         op_mod[0x10];
8574 
8575 	u8         reserved_2[0x40];
8576 };
8577 
8578 struct mlx5_ifc_alloc_uar_out_bits {
8579 	u8         status[0x8];
8580 	u8         reserved_0[0x18];
8581 
8582 	u8         syndrome[0x20];
8583 
8584 	u8         reserved_1[0x8];
8585 	u8         uar[0x18];
8586 
8587 	u8         reserved_2[0x20];
8588 };
8589 
8590 struct mlx5_ifc_alloc_uar_in_bits {
8591 	u8         opcode[0x10];
8592 	u8         uid[0x10];
8593 
8594 	u8         reserved_1[0x10];
8595 	u8         op_mod[0x10];
8596 
8597 	u8         reserved_2[0x40];
8598 };
8599 
8600 struct mlx5_ifc_alloc_transport_domain_out_bits {
8601 	u8         status[0x8];
8602 	u8         reserved_0[0x18];
8603 
8604 	u8         syndrome[0x20];
8605 
8606 	u8         reserved_1[0x8];
8607 	u8         transport_domain[0x18];
8608 
8609 	u8         reserved_2[0x20];
8610 };
8611 
8612 struct mlx5_ifc_alloc_transport_domain_in_bits {
8613 	u8         opcode[0x10];
8614 	u8         uid[0x10];
8615 
8616 	u8         reserved_1[0x10];
8617 	u8         op_mod[0x10];
8618 
8619 	u8         reserved_2[0x40];
8620 };
8621 
8622 struct mlx5_ifc_alloc_q_counter_out_bits {
8623 	u8         status[0x8];
8624 	u8         reserved_0[0x18];
8625 
8626 	u8         syndrome[0x20];
8627 
8628 	u8         reserved_1[0x18];
8629 	u8         counter_set_id[0x8];
8630 
8631 	u8         reserved_2[0x20];
8632 };
8633 
8634 struct mlx5_ifc_alloc_q_counter_in_bits {
8635 	u8         opcode[0x10];
8636 	u8         uid[0x10];
8637 
8638 	u8         reserved_1[0x10];
8639 	u8         op_mod[0x10];
8640 
8641 	u8         reserved_2[0x40];
8642 };
8643 
8644 struct mlx5_ifc_alloc_pd_out_bits {
8645 	u8         status[0x8];
8646 	u8         reserved_0[0x18];
8647 
8648 	u8         syndrome[0x20];
8649 
8650 	u8         reserved_1[0x8];
8651 	u8         pd[0x18];
8652 
8653 	u8         reserved_2[0x20];
8654 };
8655 
8656 struct mlx5_ifc_alloc_pd_in_bits {
8657 	u8         opcode[0x10];
8658 	u8         uid[0x10];
8659 
8660 	u8         reserved_1[0x10];
8661 	u8         op_mod[0x10];
8662 
8663 	u8         reserved_2[0x40];
8664 };
8665 
8666 struct mlx5_ifc_alloc_flow_counter_out_bits {
8667 	u8         status[0x8];
8668 	u8         reserved_at_8[0x18];
8669 
8670 	u8         syndrome[0x20];
8671 
8672 	u8         flow_counter_id[0x20];
8673 
8674 	u8         reserved_at_60[0x20];
8675 };
8676 
8677 struct mlx5_ifc_alloc_flow_counter_in_bits {
8678 	u8         opcode[0x10];
8679 	u8         reserved_at_10[0x10];
8680 
8681 	u8         reserved_at_20[0x10];
8682 	u8         op_mod[0x10];
8683 
8684 	u8         reserved_at_40[0x38];
8685 	u8         flow_counter_bulk[0x8];
8686 };
8687 
8688 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8689 	u8         status[0x8];
8690 	u8         reserved_0[0x18];
8691 
8692 	u8         syndrome[0x20];
8693 
8694 	u8         reserved_1[0x40];
8695 };
8696 
8697 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8698 	u8         opcode[0x10];
8699 	u8         reserved_0[0x10];
8700 
8701 	u8         reserved_1[0x10];
8702 	u8         op_mod[0x10];
8703 
8704 	u8         reserved_2[0x20];
8705 
8706 	u8         reserved_3[0x10];
8707 	u8         vxlan_udp_port[0x10];
8708 };
8709 
8710 struct mlx5_ifc_activate_tracer_out_bits {
8711 	u8         status[0x8];
8712 	u8         reserved_0[0x18];
8713 
8714 	u8         syndrome[0x20];
8715 
8716 	u8         reserved_1[0x40];
8717 };
8718 
8719 struct mlx5_ifc_activate_tracer_in_bits {
8720 	u8         opcode[0x10];
8721 	u8         reserved_0[0x10];
8722 
8723 	u8         reserved_1[0x10];
8724 	u8         op_mod[0x10];
8725 
8726 	u8         mkey[0x20];
8727 
8728 	u8         reserved_2[0x20];
8729 };
8730 
8731 struct mlx5_ifc_set_rate_limit_out_bits {
8732 	u8         status[0x8];
8733 	u8         reserved_at_8[0x18];
8734 
8735 	u8         syndrome[0x20];
8736 
8737 	u8         reserved_at_40[0x40];
8738 };
8739 
8740 struct mlx5_ifc_set_rate_limit_in_bits {
8741 	u8         opcode[0x10];
8742 	u8         uid[0x10];
8743 
8744 	u8         reserved_at_20[0x10];
8745 	u8         op_mod[0x10];
8746 
8747 	u8         reserved_at_40[0x10];
8748 	u8         rate_limit_index[0x10];
8749 
8750 	u8         reserved_at_60[0x20];
8751 
8752 	u8         rate_limit[0x20];
8753 
8754 	u8         burst_upper_bound[0x20];
8755 
8756 	u8         reserved_at_c0[0x10];
8757 	u8         typical_packet_size[0x10];
8758 
8759 	u8         reserved_at_e0[0x120];
8760 };
8761 
8762 struct mlx5_ifc_access_register_out_bits {
8763 	u8         status[0x8];
8764 	u8         reserved_0[0x18];
8765 
8766 	u8         syndrome[0x20];
8767 
8768 	u8         reserved_1[0x40];
8769 
8770 	u8         register_data[0][0x20];
8771 };
8772 
8773 enum {
8774 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8775 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8776 };
8777 
8778 struct mlx5_ifc_access_register_in_bits {
8779 	u8         opcode[0x10];
8780 	u8         reserved_0[0x10];
8781 
8782 	u8         reserved_1[0x10];
8783 	u8         op_mod[0x10];
8784 
8785 	u8         reserved_2[0x10];
8786 	u8         register_id[0x10];
8787 
8788 	u8         argument[0x20];
8789 
8790 	u8         register_data[0][0x20];
8791 };
8792 
8793 struct mlx5_ifc_sltp_reg_bits {
8794 	u8         status[0x4];
8795 	u8         version[0x4];
8796 	u8         local_port[0x8];
8797 	u8         pnat[0x2];
8798 	u8         reserved_0[0x2];
8799 	u8         lane[0x4];
8800 	u8         reserved_1[0x8];
8801 
8802 	u8         reserved_2[0x20];
8803 
8804 	u8         reserved_3[0x7];
8805 	u8         polarity[0x1];
8806 	u8         ob_tap0[0x8];
8807 	u8         ob_tap1[0x8];
8808 	u8         ob_tap2[0x8];
8809 
8810 	u8         reserved_4[0xc];
8811 	u8         ob_preemp_mode[0x4];
8812 	u8         ob_reg[0x8];
8813 	u8         ob_bias[0x8];
8814 
8815 	u8         reserved_5[0x20];
8816 };
8817 
8818 struct mlx5_ifc_slrp_reg_bits {
8819 	u8         status[0x4];
8820 	u8         version[0x4];
8821 	u8         local_port[0x8];
8822 	u8         pnat[0x2];
8823 	u8         reserved_0[0x2];
8824 	u8         lane[0x4];
8825 	u8         reserved_1[0x8];
8826 
8827 	u8         ib_sel[0x2];
8828 	u8         reserved_2[0x11];
8829 	u8         dp_sel[0x1];
8830 	u8         dp90sel[0x4];
8831 	u8         mix90phase[0x8];
8832 
8833 	u8         ffe_tap0[0x8];
8834 	u8         ffe_tap1[0x8];
8835 	u8         ffe_tap2[0x8];
8836 	u8         ffe_tap3[0x8];
8837 
8838 	u8         ffe_tap4[0x8];
8839 	u8         ffe_tap5[0x8];
8840 	u8         ffe_tap6[0x8];
8841 	u8         ffe_tap7[0x8];
8842 
8843 	u8         ffe_tap8[0x8];
8844 	u8         mixerbias_tap_amp[0x8];
8845 	u8         reserved_3[0x7];
8846 	u8         ffe_tap_en[0x9];
8847 
8848 	u8         ffe_tap_offset0[0x8];
8849 	u8         ffe_tap_offset1[0x8];
8850 	u8         slicer_offset0[0x10];
8851 
8852 	u8         mixer_offset0[0x10];
8853 	u8         mixer_offset1[0x10];
8854 
8855 	u8         mixerbgn_inp[0x8];
8856 	u8         mixerbgn_inn[0x8];
8857 	u8         mixerbgn_refp[0x8];
8858 	u8         mixerbgn_refn[0x8];
8859 
8860 	u8         sel_slicer_lctrl_h[0x1];
8861 	u8         sel_slicer_lctrl_l[0x1];
8862 	u8         reserved_4[0x1];
8863 	u8         ref_mixer_vreg[0x5];
8864 	u8         slicer_gctrl[0x8];
8865 	u8         lctrl_input[0x8];
8866 	u8         mixer_offset_cm1[0x8];
8867 
8868 	u8         common_mode[0x6];
8869 	u8         reserved_5[0x1];
8870 	u8         mixer_offset_cm0[0x9];
8871 	u8         reserved_6[0x7];
8872 	u8         slicer_offset_cm[0x9];
8873 };
8874 
8875 struct mlx5_ifc_slrg_reg_bits {
8876 	u8         status[0x4];
8877 	u8         version[0x4];
8878 	u8         local_port[0x8];
8879 	u8         pnat[0x2];
8880 	u8         reserved_0[0x2];
8881 	u8         lane[0x4];
8882 	u8         reserved_1[0x8];
8883 
8884 	u8         time_to_link_up[0x10];
8885 	u8         reserved_2[0xc];
8886 	u8         grade_lane_speed[0x4];
8887 
8888 	u8         grade_version[0x8];
8889 	u8         grade[0x18];
8890 
8891 	u8         reserved_3[0x4];
8892 	u8         height_grade_type[0x4];
8893 	u8         height_grade[0x18];
8894 
8895 	u8         height_dz[0x10];
8896 	u8         height_dv[0x10];
8897 
8898 	u8         reserved_4[0x10];
8899 	u8         height_sigma[0x10];
8900 
8901 	u8         reserved_5[0x20];
8902 
8903 	u8         reserved_6[0x4];
8904 	u8         phase_grade_type[0x4];
8905 	u8         phase_grade[0x18];
8906 
8907 	u8         reserved_7[0x8];
8908 	u8         phase_eo_pos[0x8];
8909 	u8         reserved_8[0x8];
8910 	u8         phase_eo_neg[0x8];
8911 
8912 	u8         ffe_set_tested[0x10];
8913 	u8         test_errors_per_lane[0x10];
8914 };
8915 
8916 struct mlx5_ifc_pvlc_reg_bits {
8917 	u8         reserved_0[0x8];
8918 	u8         local_port[0x8];
8919 	u8         reserved_1[0x10];
8920 
8921 	u8         reserved_2[0x1c];
8922 	u8         vl_hw_cap[0x4];
8923 
8924 	u8         reserved_3[0x1c];
8925 	u8         vl_admin[0x4];
8926 
8927 	u8         reserved_4[0x1c];
8928 	u8         vl_operational[0x4];
8929 };
8930 
8931 struct mlx5_ifc_pude_reg_bits {
8932 	u8         swid[0x8];
8933 	u8         local_port[0x8];
8934 	u8         reserved_0[0x4];
8935 	u8         admin_status[0x4];
8936 	u8         reserved_1[0x4];
8937 	u8         oper_status[0x4];
8938 
8939 	u8         reserved_2[0x60];
8940 };
8941 
8942 enum {
8943 	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
8944 	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
8945 };
8946 
8947 struct mlx5_ifc_ptys_reg_bits {
8948 	u8         reserved_0[0x1];
8949 	u8         an_disable_admin[0x1];
8950 	u8         an_disable_cap[0x1];
8951 	u8         reserved_1[0x4];
8952 	u8         force_tx_aba_param[0x1];
8953 	u8         local_port[0x8];
8954 	u8         reserved_2[0xd];
8955 	u8         proto_mask[0x3];
8956 
8957 	u8         an_status[0x4];
8958 	u8         reserved_3[0xc];
8959 	u8         data_rate_oper[0x10];
8960 
8961 	u8         ext_eth_proto_capability[0x20];
8962 
8963 	u8         eth_proto_capability[0x20];
8964 
8965 	u8         ib_link_width_capability[0x10];
8966 	u8         ib_proto_capability[0x10];
8967 
8968 	u8         ext_eth_proto_admin[0x20];
8969 
8970 	u8         eth_proto_admin[0x20];
8971 
8972 	u8         ib_link_width_admin[0x10];
8973 	u8         ib_proto_admin[0x10];
8974 
8975 	u8         ext_eth_proto_oper[0x20];
8976 
8977 	u8         eth_proto_oper[0x20];
8978 
8979 	u8         ib_link_width_oper[0x10];
8980 	u8         ib_proto_oper[0x10];
8981 
8982 	u8         reserved_4[0x1c];
8983 	u8         connector_type[0x4];
8984 
8985 	u8         eth_proto_lp_advertise[0x20];
8986 
8987 	u8         reserved_5[0x60];
8988 };
8989 
8990 struct mlx5_ifc_ptas_reg_bits {
8991 	u8         reserved_0[0x20];
8992 
8993 	u8         algorithm_options[0x10];
8994 	u8         reserved_1[0x4];
8995 	u8         repetitions_mode[0x4];
8996 	u8         num_of_repetitions[0x8];
8997 
8998 	u8         grade_version[0x8];
8999 	u8         height_grade_type[0x4];
9000 	u8         phase_grade_type[0x4];
9001 	u8         height_grade_weight[0x8];
9002 	u8         phase_grade_weight[0x8];
9003 
9004 	u8         gisim_measure_bits[0x10];
9005 	u8         adaptive_tap_measure_bits[0x10];
9006 
9007 	u8         ber_bath_high_error_threshold[0x10];
9008 	u8         ber_bath_mid_error_threshold[0x10];
9009 
9010 	u8         ber_bath_low_error_threshold[0x10];
9011 	u8         one_ratio_high_threshold[0x10];
9012 
9013 	u8         one_ratio_high_mid_threshold[0x10];
9014 	u8         one_ratio_low_mid_threshold[0x10];
9015 
9016 	u8         one_ratio_low_threshold[0x10];
9017 	u8         ndeo_error_threshold[0x10];
9018 
9019 	u8         mixer_offset_step_size[0x10];
9020 	u8         reserved_2[0x8];
9021 	u8         mix90_phase_for_voltage_bath[0x8];
9022 
9023 	u8         mixer_offset_start[0x10];
9024 	u8         mixer_offset_end[0x10];
9025 
9026 	u8         reserved_3[0x15];
9027 	u8         ber_test_time[0xb];
9028 };
9029 
9030 struct mlx5_ifc_pspa_reg_bits {
9031 	u8         swid[0x8];
9032 	u8         local_port[0x8];
9033 	u8         sub_port[0x8];
9034 	u8         reserved_0[0x8];
9035 
9036 	u8         reserved_1[0x20];
9037 };
9038 
9039 struct mlx5_ifc_ppsc_reg_bits {
9040 	u8         reserved_0[0x8];
9041 	u8         local_port[0x8];
9042 	u8         reserved_1[0x10];
9043 
9044 	u8         reserved_2[0x60];
9045 
9046 	u8         reserved_3[0x1c];
9047 	u8         wrps_admin[0x4];
9048 
9049 	u8         reserved_4[0x1c];
9050 	u8         wrps_status[0x4];
9051 
9052 	u8         up_th_vld[0x1];
9053 	u8         down_th_vld[0x1];
9054 	u8         reserved_5[0x6];
9055 	u8         up_threshold[0x8];
9056 	u8         reserved_6[0x8];
9057 	u8         down_threshold[0x8];
9058 
9059 	u8         reserved_7[0x20];
9060 
9061 	u8         reserved_8[0x1c];
9062 	u8         srps_admin[0x4];
9063 
9064 	u8         reserved_9[0x60];
9065 };
9066 
9067 struct mlx5_ifc_pplr_reg_bits {
9068 	u8         reserved_0[0x8];
9069 	u8         local_port[0x8];
9070 	u8         reserved_1[0x10];
9071 
9072 	u8         reserved_2[0x8];
9073 	u8         lb_cap[0x8];
9074 	u8         reserved_3[0x8];
9075 	u8         lb_en[0x8];
9076 };
9077 
9078 struct mlx5_ifc_pplm_reg_bits {
9079 	u8         reserved_at_0[0x8];
9080 	u8	   local_port[0x8];
9081 	u8	   reserved_at_10[0x10];
9082 
9083 	u8	   reserved_at_20[0x20];
9084 
9085 	u8	   port_profile_mode[0x8];
9086 	u8	   static_port_profile[0x8];
9087 	u8	   active_port_profile[0x8];
9088 	u8	   reserved_at_58[0x8];
9089 
9090 	u8	   retransmission_active[0x8];
9091 	u8	   fec_mode_active[0x18];
9092 
9093 	u8	   rs_fec_correction_bypass_cap[0x4];
9094 	u8	   reserved_at_84[0x8];
9095 	u8	   fec_override_cap_56g[0x4];
9096 	u8	   fec_override_cap_100g[0x4];
9097 	u8	   fec_override_cap_50g[0x4];
9098 	u8	   fec_override_cap_25g[0x4];
9099 	u8	   fec_override_cap_10g_40g[0x4];
9100 
9101 	u8	   rs_fec_correction_bypass_admin[0x4];
9102 	u8	   reserved_at_a4[0x8];
9103 	u8	   fec_override_admin_56g[0x4];
9104 	u8	   fec_override_admin_100g[0x4];
9105 	u8	   fec_override_admin_50g[0x4];
9106 	u8	   fec_override_admin_25g[0x4];
9107 	u8	   fec_override_admin_10g_40g[0x4];
9108 
9109 	u8	   fec_override_cap_400g_8x[0x10];
9110 	u8	   fec_override_cap_200g_4x[0x10];
9111 	u8	   fec_override_cap_100g_2x[0x10];
9112 	u8	   fec_override_cap_50g_1x[0x10];
9113 
9114 	u8	   fec_override_admin_400g_8x[0x10];
9115 	u8	   fec_override_admin_200g_4x[0x10];
9116 	u8	   fec_override_admin_100g_2x[0x10];
9117 	u8	   fec_override_admin_50g_1x[0x10];
9118 
9119 	u8	   reserved_at_140[0x140];
9120 };
9121 
9122 struct mlx5_ifc_ppll_reg_bits {
9123 	u8         num_pll_groups[0x8];
9124 	u8         pll_group[0x8];
9125 	u8         reserved_0[0x4];
9126 	u8         num_plls[0x4];
9127 	u8         reserved_1[0x8];
9128 
9129 	u8         reserved_2[0x1f];
9130 	u8         ae[0x1];
9131 
9132 	u8         pll_status[4][0x40];
9133 };
9134 
9135 struct mlx5_ifc_ppad_reg_bits {
9136 	u8         reserved_0[0x3];
9137 	u8         single_mac[0x1];
9138 	u8         reserved_1[0x4];
9139 	u8         local_port[0x8];
9140 	u8         mac_47_32[0x10];
9141 
9142 	u8         mac_31_0[0x20];
9143 
9144 	u8         reserved_2[0x40];
9145 };
9146 
9147 struct mlx5_ifc_pmtu_reg_bits {
9148 	u8         reserved_0[0x8];
9149 	u8         local_port[0x8];
9150 	u8         reserved_1[0x10];
9151 
9152 	u8         max_mtu[0x10];
9153 	u8         reserved_2[0x10];
9154 
9155 	u8         admin_mtu[0x10];
9156 	u8         reserved_3[0x10];
9157 
9158 	u8         oper_mtu[0x10];
9159 	u8         reserved_4[0x10];
9160 };
9161 
9162 struct mlx5_ifc_pmpr_reg_bits {
9163 	u8         reserved_0[0x8];
9164 	u8         module[0x8];
9165 	u8         reserved_1[0x10];
9166 
9167 	u8         reserved_2[0x18];
9168 	u8         attenuation_5g[0x8];
9169 
9170 	u8         reserved_3[0x18];
9171 	u8         attenuation_7g[0x8];
9172 
9173 	u8         reserved_4[0x18];
9174 	u8         attenuation_12g[0x8];
9175 };
9176 
9177 struct mlx5_ifc_pmpe_reg_bits {
9178 	u8         reserved_0[0x8];
9179 	u8         module[0x8];
9180 	u8         reserved_1[0xc];
9181 	u8         module_status[0x4];
9182 
9183 	u8         reserved_2[0x14];
9184 	u8         error_type[0x4];
9185 	u8         reserved_3[0x8];
9186 
9187 	u8         reserved_4[0x40];
9188 };
9189 
9190 struct mlx5_ifc_pmpc_reg_bits {
9191 	u8         module_state_updated[32][0x8];
9192 };
9193 
9194 struct mlx5_ifc_pmlpn_reg_bits {
9195 	u8         reserved_0[0x4];
9196 	u8         mlpn_status[0x4];
9197 	u8         local_port[0x8];
9198 	u8         reserved_1[0x10];
9199 
9200 	u8         e[0x1];
9201 	u8         reserved_2[0x1f];
9202 };
9203 
9204 struct mlx5_ifc_pmlp_reg_bits {
9205 	u8         rxtx[0x1];
9206 	u8         reserved_0[0x7];
9207 	u8         local_port[0x8];
9208 	u8         reserved_1[0x8];
9209 	u8         width[0x8];
9210 
9211 	u8         lane0_module_mapping[0x20];
9212 
9213 	u8         lane1_module_mapping[0x20];
9214 
9215 	u8         lane2_module_mapping[0x20];
9216 
9217 	u8         lane3_module_mapping[0x20];
9218 
9219 	u8         reserved_2[0x160];
9220 };
9221 
9222 struct mlx5_ifc_pmaos_reg_bits {
9223 	u8         reserved_0[0x8];
9224 	u8         module[0x8];
9225 	u8         reserved_1[0x4];
9226 	u8         admin_status[0x4];
9227 	u8         reserved_2[0x4];
9228 	u8         oper_status[0x4];
9229 
9230 	u8         ase[0x1];
9231 	u8         ee[0x1];
9232 	u8         reserved_3[0x12];
9233 	u8         error_type[0x4];
9234 	u8         reserved_4[0x6];
9235 	u8         e[0x2];
9236 
9237 	u8         reserved_5[0x40];
9238 };
9239 
9240 struct mlx5_ifc_plpc_reg_bits {
9241 	u8         reserved_0[0x4];
9242 	u8         profile_id[0xc];
9243 	u8         reserved_1[0x4];
9244 	u8         proto_mask[0x4];
9245 	u8         reserved_2[0x8];
9246 
9247 	u8         reserved_3[0x10];
9248 	u8         lane_speed[0x10];
9249 
9250 	u8         reserved_4[0x17];
9251 	u8         lpbf[0x1];
9252 	u8         fec_mode_policy[0x8];
9253 
9254 	u8         retransmission_capability[0x8];
9255 	u8         fec_mode_capability[0x18];
9256 
9257 	u8         retransmission_support_admin[0x8];
9258 	u8         fec_mode_support_admin[0x18];
9259 
9260 	u8         retransmission_request_admin[0x8];
9261 	u8         fec_mode_request_admin[0x18];
9262 
9263 	u8         reserved_5[0x80];
9264 };
9265 
9266 struct mlx5_ifc_pll_status_data_bits {
9267 	u8         reserved_0[0x1];
9268 	u8         lock_cal[0x1];
9269 	u8         lock_status[0x2];
9270 	u8         reserved_1[0x2];
9271 	u8         algo_f_ctrl[0xa];
9272 	u8         analog_algo_num_var[0x6];
9273 	u8         f_ctrl_measure[0xa];
9274 
9275 	u8         reserved_2[0x2];
9276 	u8         analog_var[0x6];
9277 	u8         reserved_3[0x2];
9278 	u8         high_var[0x6];
9279 	u8         reserved_4[0x2];
9280 	u8         low_var[0x6];
9281 	u8         reserved_5[0x2];
9282 	u8         mid_val[0x6];
9283 };
9284 
9285 struct mlx5_ifc_plib_reg_bits {
9286 	u8         reserved_0[0x8];
9287 	u8         local_port[0x8];
9288 	u8         reserved_1[0x8];
9289 	u8         ib_port[0x8];
9290 
9291 	u8         reserved_2[0x60];
9292 };
9293 
9294 struct mlx5_ifc_plbf_reg_bits {
9295 	u8         reserved_0[0x8];
9296 	u8         local_port[0x8];
9297 	u8         reserved_1[0xd];
9298 	u8         lbf_mode[0x3];
9299 
9300 	u8         reserved_2[0x20];
9301 };
9302 
9303 struct mlx5_ifc_pipg_reg_bits {
9304 	u8         reserved_0[0x8];
9305 	u8         local_port[0x8];
9306 	u8         reserved_1[0x10];
9307 
9308 	u8         dic[0x1];
9309 	u8         reserved_2[0x19];
9310 	u8         ipg[0x4];
9311 	u8         reserved_3[0x2];
9312 };
9313 
9314 struct mlx5_ifc_pifr_reg_bits {
9315 	u8         reserved_0[0x8];
9316 	u8         local_port[0x8];
9317 	u8         reserved_1[0x10];
9318 
9319 	u8         reserved_2[0xe0];
9320 
9321 	u8         port_filter[8][0x20];
9322 
9323 	u8         port_filter_update_en[8][0x20];
9324 };
9325 
9326 struct mlx5_ifc_phys_layer_cntrs_bits {
9327 	u8         time_since_last_clear_high[0x20];
9328 
9329 	u8         time_since_last_clear_low[0x20];
9330 
9331 	u8         symbol_errors_high[0x20];
9332 
9333 	u8         symbol_errors_low[0x20];
9334 
9335 	u8         sync_headers_errors_high[0x20];
9336 
9337 	u8         sync_headers_errors_low[0x20];
9338 
9339 	u8         edpl_bip_errors_lane0_high[0x20];
9340 
9341 	u8         edpl_bip_errors_lane0_low[0x20];
9342 
9343 	u8         edpl_bip_errors_lane1_high[0x20];
9344 
9345 	u8         edpl_bip_errors_lane1_low[0x20];
9346 
9347 	u8         edpl_bip_errors_lane2_high[0x20];
9348 
9349 	u8         edpl_bip_errors_lane2_low[0x20];
9350 
9351 	u8         edpl_bip_errors_lane3_high[0x20];
9352 
9353 	u8         edpl_bip_errors_lane3_low[0x20];
9354 
9355 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
9356 
9357 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
9358 
9359 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
9360 
9361 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
9362 
9363 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
9364 
9365 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
9366 
9367 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
9368 
9369 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
9370 
9371 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
9372 
9373 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
9374 
9375 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
9376 
9377 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
9378 
9379 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
9380 
9381 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
9382 
9383 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
9384 
9385 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
9386 
9387 	u8         rs_fec_corrected_blocks_high[0x20];
9388 
9389 	u8         rs_fec_corrected_blocks_low[0x20];
9390 
9391 	u8         rs_fec_uncorrectable_blocks_high[0x20];
9392 
9393 	u8         rs_fec_uncorrectable_blocks_low[0x20];
9394 
9395 	u8         rs_fec_no_errors_blocks_high[0x20];
9396 
9397 	u8         rs_fec_no_errors_blocks_low[0x20];
9398 
9399 	u8         rs_fec_single_error_blocks_high[0x20];
9400 
9401 	u8         rs_fec_single_error_blocks_low[0x20];
9402 
9403 	u8         rs_fec_corrected_symbols_total_high[0x20];
9404 
9405 	u8         rs_fec_corrected_symbols_total_low[0x20];
9406 
9407 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
9408 
9409 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
9410 
9411 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
9412 
9413 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
9414 
9415 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
9416 
9417 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
9418 
9419 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
9420 
9421 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
9422 
9423 	u8         link_down_events[0x20];
9424 
9425 	u8         successful_recovery_events[0x20];
9426 
9427 	u8         reserved_0[0x180];
9428 };
9429 
9430 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
9431 	u8	   symbol_error_counter[0x10];
9432 
9433 	u8         link_error_recovery_counter[0x8];
9434 
9435 	u8         link_downed_counter[0x8];
9436 
9437 	u8         port_rcv_errors[0x10];
9438 
9439 	u8         port_rcv_remote_physical_errors[0x10];
9440 
9441 	u8         port_rcv_switch_relay_errors[0x10];
9442 
9443 	u8         port_xmit_discards[0x10];
9444 
9445 	u8         port_xmit_constraint_errors[0x8];
9446 
9447 	u8         port_rcv_constraint_errors[0x8];
9448 
9449 	u8         reserved_at_70[0x8];
9450 
9451 	u8         link_overrun_errors[0x8];
9452 
9453 	u8	   reserved_at_80[0x10];
9454 
9455 	u8         vl_15_dropped[0x10];
9456 
9457 	u8	   reserved_at_a0[0xa0];
9458 };
9459 
9460 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
9461 	u8         time_since_last_clear_high[0x20];
9462 
9463 	u8         time_since_last_clear_low[0x20];
9464 
9465 	u8         phy_received_bits_high[0x20];
9466 
9467 	u8         phy_received_bits_low[0x20];
9468 
9469 	u8         phy_symbol_errors_high[0x20];
9470 
9471 	u8         phy_symbol_errors_low[0x20];
9472 
9473 	u8         phy_corrected_bits_high[0x20];
9474 
9475 	u8         phy_corrected_bits_low[0x20];
9476 
9477 	u8         phy_corrected_bits_lane0_high[0x20];
9478 
9479 	u8         phy_corrected_bits_lane0_low[0x20];
9480 
9481 	u8         phy_corrected_bits_lane1_high[0x20];
9482 
9483 	u8         phy_corrected_bits_lane1_low[0x20];
9484 
9485 	u8         phy_corrected_bits_lane2_high[0x20];
9486 
9487 	u8         phy_corrected_bits_lane2_low[0x20];
9488 
9489 	u8         phy_corrected_bits_lane3_high[0x20];
9490 
9491 	u8         phy_corrected_bits_lane3_low[0x20];
9492 
9493 	u8         reserved_at_200[0x5c0];
9494 };
9495 
9496 struct mlx5_ifc_infiniband_port_cntrs_bits {
9497 	u8         symbol_error_counter[0x10];
9498 	u8         link_error_recovery_counter[0x8];
9499 	u8         link_downed_counter[0x8];
9500 
9501 	u8         port_rcv_errors[0x10];
9502 	u8         port_rcv_remote_physical_errors[0x10];
9503 
9504 	u8         port_rcv_switch_relay_errors[0x10];
9505 	u8         port_xmit_discards[0x10];
9506 
9507 	u8         port_xmit_constraint_errors[0x8];
9508 	u8         port_rcv_constraint_errors[0x8];
9509 	u8         reserved_0[0x8];
9510 	u8         local_link_integrity_errors[0x4];
9511 	u8         excessive_buffer_overrun_errors[0x4];
9512 
9513 	u8         reserved_1[0x10];
9514 	u8         vl_15_dropped[0x10];
9515 
9516 	u8         port_xmit_data[0x20];
9517 
9518 	u8         port_rcv_data[0x20];
9519 
9520 	u8         port_xmit_pkts[0x20];
9521 
9522 	u8         port_rcv_pkts[0x20];
9523 
9524 	u8         port_xmit_wait[0x20];
9525 
9526 	u8         reserved_2[0x680];
9527 };
9528 
9529 struct mlx5_ifc_phrr_reg_bits {
9530 	u8         clr[0x1];
9531 	u8         reserved_0[0x7];
9532 	u8         local_port[0x8];
9533 	u8         reserved_1[0x10];
9534 
9535 	u8         hist_group[0x8];
9536 	u8         reserved_2[0x10];
9537 	u8         hist_id[0x8];
9538 
9539 	u8         reserved_3[0x40];
9540 
9541 	u8         time_since_last_clear_high[0x20];
9542 
9543 	u8         time_since_last_clear_low[0x20];
9544 
9545 	u8         bin[10][0x20];
9546 };
9547 
9548 struct mlx5_ifc_phbr_for_prio_reg_bits {
9549 	u8         reserved_0[0x18];
9550 	u8         prio[0x8];
9551 };
9552 
9553 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
9554 	u8         reserved_0[0x18];
9555 	u8         tclass[0x8];
9556 };
9557 
9558 struct mlx5_ifc_phbr_binding_reg_bits {
9559 	u8         opcode[0x4];
9560 	u8         reserved_0[0x4];
9561 	u8         local_port[0x8];
9562 	u8         pnat[0x2];
9563 	u8         reserved_1[0xe];
9564 
9565 	u8         hist_group[0x8];
9566 	u8         reserved_2[0x10];
9567 	u8         hist_id[0x8];
9568 
9569 	u8         reserved_3[0x10];
9570 	u8         hist_type[0x10];
9571 
9572 	u8         hist_parameters[0x20];
9573 
9574 	u8         hist_min_value[0x20];
9575 
9576 	u8         hist_max_value[0x20];
9577 
9578 	u8         sample_time[0x20];
9579 };
9580 
9581 enum {
9582 	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
9583 	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
9584 };
9585 
9586 struct mlx5_ifc_pfcc_reg_bits {
9587 	u8         dcbx_operation_type[0x2];
9588 	u8         cap_local_admin[0x1];
9589 	u8         cap_remote_admin[0x1];
9590 	u8         reserved_0[0x4];
9591 	u8         local_port[0x8];
9592 	u8         pnat[0x2];
9593 	u8         reserved_1[0xc];
9594 	u8         shl_cap[0x1];
9595 	u8         shl_opr[0x1];
9596 
9597 	u8         ppan[0x4];
9598 	u8         reserved_2[0x4];
9599 	u8         prio_mask_tx[0x8];
9600 	u8         reserved_3[0x8];
9601 	u8         prio_mask_rx[0x8];
9602 
9603 	u8         pptx[0x1];
9604 	u8         aptx[0x1];
9605 	u8         reserved_4[0x6];
9606 	u8         pfctx[0x8];
9607 	u8         reserved_5[0x8];
9608 	u8         cbftx[0x8];
9609 
9610 	u8         pprx[0x1];
9611 	u8         aprx[0x1];
9612 	u8         reserved_6[0x6];
9613 	u8         pfcrx[0x8];
9614 	u8         reserved_7[0x8];
9615 	u8         cbfrx[0x8];
9616 
9617 	u8         device_stall_minor_watermark[0x10];
9618 	u8         device_stall_critical_watermark[0x10];
9619 
9620 	u8         reserved_8[0x60];
9621 };
9622 
9623 struct mlx5_ifc_pelc_reg_bits {
9624 	u8         op[0x4];
9625 	u8         reserved_0[0x4];
9626 	u8         local_port[0x8];
9627 	u8         reserved_1[0x10];
9628 
9629 	u8         op_admin[0x8];
9630 	u8         op_capability[0x8];
9631 	u8         op_request[0x8];
9632 	u8         op_active[0x8];
9633 
9634 	u8         admin[0x40];
9635 
9636 	u8         capability[0x40];
9637 
9638 	u8         request[0x40];
9639 
9640 	u8         active[0x40];
9641 
9642 	u8         reserved_2[0x80];
9643 };
9644 
9645 struct mlx5_ifc_peir_reg_bits {
9646 	u8         reserved_0[0x8];
9647 	u8         local_port[0x8];
9648 	u8         reserved_1[0x10];
9649 
9650 	u8         reserved_2[0xc];
9651 	u8         error_count[0x4];
9652 	u8         reserved_3[0x10];
9653 
9654 	u8         reserved_4[0xc];
9655 	u8         lane[0x4];
9656 	u8         reserved_5[0x8];
9657 	u8         error_type[0x8];
9658 };
9659 
9660 struct mlx5_ifc_qcam_access_reg_cap_mask {
9661 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9662 	u8         qpdpm[0x1];
9663 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9664 	u8         qdpm[0x1];
9665 	u8         qpts[0x1];
9666 	u8         qcap[0x1];
9667 	u8         qcam_access_reg_cap_mask_0[0x1];
9668 };
9669 
9670 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9671 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9672 	u8         qpts_trust_both[0x1];
9673 };
9674 
9675 struct mlx5_ifc_qcam_reg_bits {
9676 	u8         reserved_at_0[0x8];
9677 	u8         feature_group[0x8];
9678 	u8         reserved_at_10[0x8];
9679 	u8         access_reg_group[0x8];
9680 	u8         reserved_at_20[0x20];
9681 
9682 	union {
9683 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9684 		u8  reserved_at_0[0x80];
9685 	} qos_access_reg_cap_mask;
9686 
9687 	u8         reserved_at_c0[0x80];
9688 
9689 	union {
9690 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9691 		u8  reserved_at_0[0x80];
9692 	} qos_feature_cap_mask;
9693 
9694 	u8         reserved_at_1c0[0x80];
9695 };
9696 
9697 struct mlx5_ifc_pcam_enhanced_features_bits {
9698 	u8         reserved_at_0[0x6d];
9699 	u8         rx_icrc_encapsulated_counter[0x1];
9700 	u8	   reserved_at_6e[0x4];
9701 	u8         ptys_extended_ethernet[0x1];
9702 	u8	   reserved_at_73[0x3];
9703 	u8         pfcc_mask[0x1];
9704 	u8         reserved_at_77[0x3];
9705 	u8         per_lane_error_counters[0x1];
9706 	u8         rx_buffer_fullness_counters[0x1];
9707 	u8         ptys_connector_type[0x1];
9708 	u8         reserved_at_7d[0x1];
9709 	u8         ppcnt_discard_group[0x1];
9710 	u8         ppcnt_statistical_group[0x1];
9711 };
9712 
9713 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9714 	u8         port_access_reg_cap_mask_127_to_96[0x20];
9715 	u8         port_access_reg_cap_mask_95_to_64[0x20];
9716 
9717 	u8         reserved_at_40[0xe];
9718 	u8         pddr[0x1];
9719 	u8         reserved_at_4f[0xd];
9720 
9721 	u8         pplm[0x1];
9722 	u8         port_access_reg_cap_mask_34_to_32[0x3];
9723 
9724 	u8         port_access_reg_cap_mask_31_to_13[0x13];
9725 	u8         pbmc[0x1];
9726 	u8         pptb[0x1];
9727 	u8         port_access_reg_cap_mask_10_to_09[0x2];
9728 	u8         ppcnt[0x1];
9729 	u8         port_access_reg_cap_mask_07_to_00[0x8];
9730 };
9731 
9732 struct mlx5_ifc_pcam_reg_bits {
9733 	u8         reserved_at_0[0x8];
9734 	u8         feature_group[0x8];
9735 	u8         reserved_at_10[0x8];
9736 	u8         access_reg_group[0x8];
9737 
9738 	u8         reserved_at_20[0x20];
9739 
9740 	union {
9741 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9742 		u8         reserved_at_0[0x80];
9743 	} port_access_reg_cap_mask;
9744 
9745 	u8         reserved_at_c0[0x80];
9746 
9747 	union {
9748 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9749 		u8         reserved_at_0[0x80];
9750 	} feature_cap_mask;
9751 
9752 	u8         reserved_at_1c0[0xc0];
9753 };
9754 
9755 struct mlx5_ifc_mcam_enhanced_features_bits {
9756 	u8         reserved_at_0[0x6e];
9757 	u8         pcie_status_and_power[0x1];
9758 	u8         reserved_at_111[0x10];
9759 	u8         pcie_performance_group[0x1];
9760 };
9761 
9762 struct mlx5_ifc_mcam_access_reg_bits {
9763 	u8         reserved_at_0[0x1c];
9764 	u8         mcda[0x1];
9765 	u8         mcc[0x1];
9766 	u8         mcqi[0x1];
9767 	u8         reserved_at_1f[0x1];
9768 
9769 	u8         regs_95_to_64[0x20];
9770 	u8         regs_63_to_32[0x20];
9771 	u8         regs_31_to_0[0x20];
9772 };
9773 
9774 struct mlx5_ifc_mcam_reg_bits {
9775 	u8         reserved_at_0[0x8];
9776 	u8         feature_group[0x8];
9777 	u8         reserved_at_10[0x8];
9778 	u8         access_reg_group[0x8];
9779 
9780 	u8         reserved_at_20[0x20];
9781 
9782 	union {
9783 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9784 		u8         reserved_at_0[0x80];
9785 	} mng_access_reg_cap_mask;
9786 
9787 	u8         reserved_at_c0[0x80];
9788 
9789 	union {
9790 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9791 		u8         reserved_at_0[0x80];
9792 	} mng_feature_cap_mask;
9793 
9794 	u8         reserved_at_1c0[0x80];
9795 };
9796 
9797 struct mlx5_ifc_pcap_reg_bits {
9798 	u8         reserved_0[0x8];
9799 	u8         local_port[0x8];
9800 	u8         reserved_1[0x10];
9801 
9802 	u8         port_capability_mask[4][0x20];
9803 };
9804 
9805 struct mlx5_ifc_pbmc_reg_bits {
9806 	u8         reserved_at_0[0x8];
9807 	u8         local_port[0x8];
9808 	u8         reserved_at_10[0x10];
9809 
9810 	u8         xoff_timer_value[0x10];
9811 	u8         xoff_refresh[0x10];
9812 
9813 	u8         reserved_at_40[0x9];
9814 	u8         fullness_threshold[0x7];
9815 	u8         port_buffer_size[0x10];
9816 
9817 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
9818 
9819 	u8         reserved_at_2e0[0x80];
9820 };
9821 
9822 struct mlx5_ifc_paos_reg_bits {
9823 	u8         swid[0x8];
9824 	u8         local_port[0x8];
9825 	u8         reserved_0[0x4];
9826 	u8         admin_status[0x4];
9827 	u8         reserved_1[0x4];
9828 	u8         oper_status[0x4];
9829 
9830 	u8         ase[0x1];
9831 	u8         ee[0x1];
9832 	u8         reserved_2[0x1c];
9833 	u8         e[0x2];
9834 
9835 	u8         reserved_3[0x40];
9836 };
9837 
9838 struct mlx5_ifc_pamp_reg_bits {
9839 	u8         reserved_0[0x8];
9840 	u8         opamp_group[0x8];
9841 	u8         reserved_1[0xc];
9842 	u8         opamp_group_type[0x4];
9843 
9844 	u8         start_index[0x10];
9845 	u8         reserved_2[0x4];
9846 	u8         num_of_indices[0xc];
9847 
9848 	u8         index_data[18][0x10];
9849 };
9850 
9851 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
9852 	u8         llr_rx_cells_high[0x20];
9853 
9854 	u8         llr_rx_cells_low[0x20];
9855 
9856 	u8         llr_rx_error_high[0x20];
9857 
9858 	u8         llr_rx_error_low[0x20];
9859 
9860 	u8         llr_rx_crc_error_high[0x20];
9861 
9862 	u8         llr_rx_crc_error_low[0x20];
9863 
9864 	u8         llr_tx_cells_high[0x20];
9865 
9866 	u8         llr_tx_cells_low[0x20];
9867 
9868 	u8         llr_tx_ret_cells_high[0x20];
9869 
9870 	u8         llr_tx_ret_cells_low[0x20];
9871 
9872 	u8         llr_tx_ret_events_high[0x20];
9873 
9874 	u8         llr_tx_ret_events_low[0x20];
9875 
9876 	u8         reserved_0[0x640];
9877 };
9878 
9879 struct mlx5_ifc_mtmp_reg_bits {
9880 	u8         i[0x1];
9881 	u8         reserved_at_1[0x18];
9882 	u8         sensor_index[0x7];
9883 
9884 	u8         reserved_at_20[0x10];
9885 	u8         temperature[0x10];
9886 
9887 	u8         mte[0x1];
9888 	u8         mtr[0x1];
9889 	u8         reserved_at_42[0x0e];
9890 	u8         max_temperature[0x10];
9891 
9892 	u8         tee[0x2];
9893 	u8         reserved_at_62[0x0e];
9894 	u8         temperature_threshold_hi[0x10];
9895 
9896 	u8         reserved_at_80[0x10];
9897 	u8         temperature_threshold_lo[0x10];
9898 
9899 	u8         reserved_at_100[0x20];
9900 
9901 	u8         sensor_name[0x40];
9902 };
9903 
9904 struct mlx5_ifc_lane_2_module_mapping_bits {
9905 	u8         reserved_0[0x6];
9906 	u8         rx_lane[0x2];
9907 	u8         reserved_1[0x6];
9908 	u8         tx_lane[0x2];
9909 	u8         reserved_2[0x8];
9910 	u8         module[0x8];
9911 };
9912 
9913 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
9914 	u8         transmit_queue_high[0x20];
9915 
9916 	u8         transmit_queue_low[0x20];
9917 
9918 	u8         reserved_0[0x780];
9919 };
9920 
9921 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
9922 	u8         no_buffer_discard_uc_high[0x20];
9923 
9924 	u8         no_buffer_discard_uc_low[0x20];
9925 
9926 	u8         wred_discard_high[0x20];
9927 
9928 	u8         wred_discard_low[0x20];
9929 
9930 	u8         reserved_0[0x740];
9931 };
9932 
9933 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
9934 	u8         rx_octets_high[0x20];
9935 
9936 	u8         rx_octets_low[0x20];
9937 
9938 	u8         reserved_0[0xc0];
9939 
9940 	u8         rx_frames_high[0x20];
9941 
9942 	u8         rx_frames_low[0x20];
9943 
9944 	u8         tx_octets_high[0x20];
9945 
9946 	u8         tx_octets_low[0x20];
9947 
9948 	u8         reserved_1[0xc0];
9949 
9950 	u8         tx_frames_high[0x20];
9951 
9952 	u8         tx_frames_low[0x20];
9953 
9954 	u8         rx_pause_high[0x20];
9955 
9956 	u8         rx_pause_low[0x20];
9957 
9958 	u8         rx_pause_duration_high[0x20];
9959 
9960 	u8         rx_pause_duration_low[0x20];
9961 
9962 	u8         tx_pause_high[0x20];
9963 
9964 	u8         tx_pause_low[0x20];
9965 
9966 	u8         tx_pause_duration_high[0x20];
9967 
9968 	u8         tx_pause_duration_low[0x20];
9969 
9970 	u8         rx_pause_transition_high[0x20];
9971 
9972 	u8         rx_pause_transition_low[0x20];
9973 
9974 	u8         rx_discards_high[0x20];
9975 
9976 	u8         rx_discards_low[0x20];
9977 
9978 	u8         device_stall_minor_watermark_cnt_high[0x20];
9979 
9980 	u8         device_stall_minor_watermark_cnt_low[0x20];
9981 
9982 	u8         device_stall_critical_watermark_cnt_high[0x20];
9983 
9984 	u8         device_stall_critical_watermark_cnt_low[0x20];
9985 
9986 	u8         reserved_2[0x340];
9987 };
9988 
9989 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9990 	u8         port_transmit_wait_high[0x20];
9991 
9992 	u8         port_transmit_wait_low[0x20];
9993 
9994 	u8         ecn_marked_high[0x20];
9995 
9996 	u8         ecn_marked_low[0x20];
9997 
9998 	u8         no_buffer_discard_mc_high[0x20];
9999 
10000 	u8         no_buffer_discard_mc_low[0x20];
10001 
10002 	u8         rx_ebp_high[0x20];
10003 
10004 	u8         rx_ebp_low[0x20];
10005 
10006 	u8         tx_ebp_high[0x20];
10007 
10008 	u8         tx_ebp_low[0x20];
10009 
10010         u8         rx_buffer_almost_full_high[0x20];
10011 
10012         u8         rx_buffer_almost_full_low[0x20];
10013 
10014         u8         rx_buffer_full_high[0x20];
10015 
10016         u8         rx_buffer_full_low[0x20];
10017 
10018         u8         rx_icrc_encapsulated_high[0x20];
10019 
10020         u8         rx_icrc_encapsulated_low[0x20];
10021 
10022 	u8         reserved_0[0x80];
10023 
10024         u8         tx_stats_pkts64octets_high[0x20];
10025 
10026         u8         tx_stats_pkts64octets_low[0x20];
10027 
10028         u8         tx_stats_pkts65to127octets_high[0x20];
10029 
10030         u8         tx_stats_pkts65to127octets_low[0x20];
10031 
10032         u8         tx_stats_pkts128to255octets_high[0x20];
10033 
10034         u8         tx_stats_pkts128to255octets_low[0x20];
10035 
10036         u8         tx_stats_pkts256to511octets_high[0x20];
10037 
10038         u8         tx_stats_pkts256to511octets_low[0x20];
10039 
10040         u8         tx_stats_pkts512to1023octets_high[0x20];
10041 
10042         u8         tx_stats_pkts512to1023octets_low[0x20];
10043 
10044         u8         tx_stats_pkts1024to1518octets_high[0x20];
10045 
10046         u8         tx_stats_pkts1024to1518octets_low[0x20];
10047 
10048         u8         tx_stats_pkts1519to2047octets_high[0x20];
10049 
10050         u8         tx_stats_pkts1519to2047octets_low[0x20];
10051 
10052         u8         tx_stats_pkts2048to4095octets_high[0x20];
10053 
10054         u8         tx_stats_pkts2048to4095octets_low[0x20];
10055 
10056         u8         tx_stats_pkts4096to8191octets_high[0x20];
10057 
10058         u8         tx_stats_pkts4096to8191octets_low[0x20];
10059 
10060         u8         tx_stats_pkts8192to10239octets_high[0x20];
10061 
10062         u8         tx_stats_pkts8192to10239octets_low[0x20];
10063 
10064 	u8         reserved_1[0x2C0];
10065 };
10066 
10067 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
10068 	u8         a_frames_transmitted_ok_high[0x20];
10069 
10070 	u8         a_frames_transmitted_ok_low[0x20];
10071 
10072 	u8         a_frames_received_ok_high[0x20];
10073 
10074 	u8         a_frames_received_ok_low[0x20];
10075 
10076 	u8         a_frame_check_sequence_errors_high[0x20];
10077 
10078 	u8         a_frame_check_sequence_errors_low[0x20];
10079 
10080 	u8         a_alignment_errors_high[0x20];
10081 
10082 	u8         a_alignment_errors_low[0x20];
10083 
10084 	u8         a_octets_transmitted_ok_high[0x20];
10085 
10086 	u8         a_octets_transmitted_ok_low[0x20];
10087 
10088 	u8         a_octets_received_ok_high[0x20];
10089 
10090 	u8         a_octets_received_ok_low[0x20];
10091 
10092 	u8         a_multicast_frames_xmitted_ok_high[0x20];
10093 
10094 	u8         a_multicast_frames_xmitted_ok_low[0x20];
10095 
10096 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
10097 
10098 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
10099 
10100 	u8         a_multicast_frames_received_ok_high[0x20];
10101 
10102 	u8         a_multicast_frames_received_ok_low[0x20];
10103 
10104 	u8         a_broadcast_frames_recieved_ok_high[0x20];
10105 
10106 	u8         a_broadcast_frames_recieved_ok_low[0x20];
10107 
10108 	u8         a_in_range_length_errors_high[0x20];
10109 
10110 	u8         a_in_range_length_errors_low[0x20];
10111 
10112 	u8         a_out_of_range_length_field_high[0x20];
10113 
10114 	u8         a_out_of_range_length_field_low[0x20];
10115 
10116 	u8         a_frame_too_long_errors_high[0x20];
10117 
10118 	u8         a_frame_too_long_errors_low[0x20];
10119 
10120 	u8         a_symbol_error_during_carrier_high[0x20];
10121 
10122 	u8         a_symbol_error_during_carrier_low[0x20];
10123 
10124 	u8         a_mac_control_frames_transmitted_high[0x20];
10125 
10126 	u8         a_mac_control_frames_transmitted_low[0x20];
10127 
10128 	u8         a_mac_control_frames_received_high[0x20];
10129 
10130 	u8         a_mac_control_frames_received_low[0x20];
10131 
10132 	u8         a_unsupported_opcodes_received_high[0x20];
10133 
10134 	u8         a_unsupported_opcodes_received_low[0x20];
10135 
10136 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
10137 
10138 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
10139 
10140 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
10141 
10142 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
10143 
10144 	u8         reserved_0[0x300];
10145 };
10146 
10147 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
10148 	u8         dot3stats_alignment_errors_high[0x20];
10149 
10150 	u8         dot3stats_alignment_errors_low[0x20];
10151 
10152 	u8         dot3stats_fcs_errors_high[0x20];
10153 
10154 	u8         dot3stats_fcs_errors_low[0x20];
10155 
10156 	u8         dot3stats_single_collision_frames_high[0x20];
10157 
10158 	u8         dot3stats_single_collision_frames_low[0x20];
10159 
10160 	u8         dot3stats_multiple_collision_frames_high[0x20];
10161 
10162 	u8         dot3stats_multiple_collision_frames_low[0x20];
10163 
10164 	u8         dot3stats_sqe_test_errors_high[0x20];
10165 
10166 	u8         dot3stats_sqe_test_errors_low[0x20];
10167 
10168 	u8         dot3stats_deferred_transmissions_high[0x20];
10169 
10170 	u8         dot3stats_deferred_transmissions_low[0x20];
10171 
10172 	u8         dot3stats_late_collisions_high[0x20];
10173 
10174 	u8         dot3stats_late_collisions_low[0x20];
10175 
10176 	u8         dot3stats_excessive_collisions_high[0x20];
10177 
10178 	u8         dot3stats_excessive_collisions_low[0x20];
10179 
10180 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
10181 
10182 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
10183 
10184 	u8         dot3stats_carrier_sense_errors_high[0x20];
10185 
10186 	u8         dot3stats_carrier_sense_errors_low[0x20];
10187 
10188 	u8         dot3stats_frame_too_longs_high[0x20];
10189 
10190 	u8         dot3stats_frame_too_longs_low[0x20];
10191 
10192 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
10193 
10194 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
10195 
10196 	u8         dot3stats_symbol_errors_high[0x20];
10197 
10198 	u8         dot3stats_symbol_errors_low[0x20];
10199 
10200 	u8         dot3control_in_unknown_opcodes_high[0x20];
10201 
10202 	u8         dot3control_in_unknown_opcodes_low[0x20];
10203 
10204 	u8         dot3in_pause_frames_high[0x20];
10205 
10206 	u8         dot3in_pause_frames_low[0x20];
10207 
10208 	u8         dot3out_pause_frames_high[0x20];
10209 
10210 	u8         dot3out_pause_frames_low[0x20];
10211 
10212 	u8         reserved_0[0x3c0];
10213 };
10214 
10215 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
10216 	u8         if_in_octets_high[0x20];
10217 
10218 	u8         if_in_octets_low[0x20];
10219 
10220 	u8         if_in_ucast_pkts_high[0x20];
10221 
10222 	u8         if_in_ucast_pkts_low[0x20];
10223 
10224 	u8         if_in_discards_high[0x20];
10225 
10226 	u8         if_in_discards_low[0x20];
10227 
10228 	u8         if_in_errors_high[0x20];
10229 
10230 	u8         if_in_errors_low[0x20];
10231 
10232 	u8         if_in_unknown_protos_high[0x20];
10233 
10234 	u8         if_in_unknown_protos_low[0x20];
10235 
10236 	u8         if_out_octets_high[0x20];
10237 
10238 	u8         if_out_octets_low[0x20];
10239 
10240 	u8         if_out_ucast_pkts_high[0x20];
10241 
10242 	u8         if_out_ucast_pkts_low[0x20];
10243 
10244 	u8         if_out_discards_high[0x20];
10245 
10246 	u8         if_out_discards_low[0x20];
10247 
10248 	u8         if_out_errors_high[0x20];
10249 
10250 	u8         if_out_errors_low[0x20];
10251 
10252 	u8         if_in_multicast_pkts_high[0x20];
10253 
10254 	u8         if_in_multicast_pkts_low[0x20];
10255 
10256 	u8         if_in_broadcast_pkts_high[0x20];
10257 
10258 	u8         if_in_broadcast_pkts_low[0x20];
10259 
10260 	u8         if_out_multicast_pkts_high[0x20];
10261 
10262 	u8         if_out_multicast_pkts_low[0x20];
10263 
10264 	u8         if_out_broadcast_pkts_high[0x20];
10265 
10266 	u8         if_out_broadcast_pkts_low[0x20];
10267 
10268 	u8         reserved_0[0x480];
10269 };
10270 
10271 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
10272 	u8         ether_stats_drop_events_high[0x20];
10273 
10274 	u8         ether_stats_drop_events_low[0x20];
10275 
10276 	u8         ether_stats_octets_high[0x20];
10277 
10278 	u8         ether_stats_octets_low[0x20];
10279 
10280 	u8         ether_stats_pkts_high[0x20];
10281 
10282 	u8         ether_stats_pkts_low[0x20];
10283 
10284 	u8         ether_stats_broadcast_pkts_high[0x20];
10285 
10286 	u8         ether_stats_broadcast_pkts_low[0x20];
10287 
10288 	u8         ether_stats_multicast_pkts_high[0x20];
10289 
10290 	u8         ether_stats_multicast_pkts_low[0x20];
10291 
10292 	u8         ether_stats_crc_align_errors_high[0x20];
10293 
10294 	u8         ether_stats_crc_align_errors_low[0x20];
10295 
10296 	u8         ether_stats_undersize_pkts_high[0x20];
10297 
10298 	u8         ether_stats_undersize_pkts_low[0x20];
10299 
10300 	u8         ether_stats_oversize_pkts_high[0x20];
10301 
10302 	u8         ether_stats_oversize_pkts_low[0x20];
10303 
10304 	u8         ether_stats_fragments_high[0x20];
10305 
10306 	u8         ether_stats_fragments_low[0x20];
10307 
10308 	u8         ether_stats_jabbers_high[0x20];
10309 
10310 	u8         ether_stats_jabbers_low[0x20];
10311 
10312 	u8         ether_stats_collisions_high[0x20];
10313 
10314 	u8         ether_stats_collisions_low[0x20];
10315 
10316 	u8         ether_stats_pkts64octets_high[0x20];
10317 
10318 	u8         ether_stats_pkts64octets_low[0x20];
10319 
10320 	u8         ether_stats_pkts65to127octets_high[0x20];
10321 
10322 	u8         ether_stats_pkts65to127octets_low[0x20];
10323 
10324 	u8         ether_stats_pkts128to255octets_high[0x20];
10325 
10326 	u8         ether_stats_pkts128to255octets_low[0x20];
10327 
10328 	u8         ether_stats_pkts256to511octets_high[0x20];
10329 
10330 	u8         ether_stats_pkts256to511octets_low[0x20];
10331 
10332 	u8         ether_stats_pkts512to1023octets_high[0x20];
10333 
10334 	u8         ether_stats_pkts512to1023octets_low[0x20];
10335 
10336 	u8         ether_stats_pkts1024to1518octets_high[0x20];
10337 
10338 	u8         ether_stats_pkts1024to1518octets_low[0x20];
10339 
10340 	u8         ether_stats_pkts1519to2047octets_high[0x20];
10341 
10342 	u8         ether_stats_pkts1519to2047octets_low[0x20];
10343 
10344 	u8         ether_stats_pkts2048to4095octets_high[0x20];
10345 
10346 	u8         ether_stats_pkts2048to4095octets_low[0x20];
10347 
10348 	u8         ether_stats_pkts4096to8191octets_high[0x20];
10349 
10350 	u8         ether_stats_pkts4096to8191octets_low[0x20];
10351 
10352 	u8         ether_stats_pkts8192to10239octets_high[0x20];
10353 
10354 	u8         ether_stats_pkts8192to10239octets_low[0x20];
10355 
10356 	u8         reserved_0[0x280];
10357 };
10358 
10359 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
10360 	u8         symbol_error_counter[0x10];
10361 	u8         link_error_recovery_counter[0x8];
10362 	u8         link_downed_counter[0x8];
10363 
10364 	u8         port_rcv_errors[0x10];
10365 	u8         port_rcv_remote_physical_errors[0x10];
10366 
10367 	u8         port_rcv_switch_relay_errors[0x10];
10368 	u8         port_xmit_discards[0x10];
10369 
10370 	u8         port_xmit_constraint_errors[0x8];
10371 	u8         port_rcv_constraint_errors[0x8];
10372 	u8         reserved_0[0x8];
10373 	u8         local_link_integrity_errors[0x4];
10374 	u8         excessive_buffer_overrun_errors[0x4];
10375 
10376 	u8         reserved_1[0x10];
10377 	u8         vl_15_dropped[0x10];
10378 
10379 	u8         port_xmit_data[0x20];
10380 
10381 	u8         port_rcv_data[0x20];
10382 
10383 	u8         port_xmit_pkts[0x20];
10384 
10385 	u8         port_rcv_pkts[0x20];
10386 
10387 	u8         port_xmit_wait[0x20];
10388 
10389 	u8         reserved_2[0x680];
10390 };
10391 
10392 struct mlx5_ifc_trc_tlb_reg_bits {
10393 	u8         reserved_0[0x80];
10394 
10395 	u8         tlb_addr[0][0x40];
10396 };
10397 
10398 struct mlx5_ifc_trc_read_fifo_reg_bits {
10399 	u8         reserved_0[0x10];
10400 	u8         requested_event_num[0x10];
10401 
10402 	u8         reserved_1[0x20];
10403 
10404 	u8         reserved_2[0x10];
10405 	u8         acual_event_num[0x10];
10406 
10407 	u8         reserved_3[0x20];
10408 
10409 	u8         event[0][0x40];
10410 };
10411 
10412 struct mlx5_ifc_trc_lock_reg_bits {
10413 	u8         reserved_0[0x1f];
10414 	u8         lock[0x1];
10415 
10416 	u8         reserved_1[0x60];
10417 };
10418 
10419 struct mlx5_ifc_trc_filter_reg_bits {
10420 	u8         status[0x1];
10421 	u8         reserved_0[0xf];
10422 	u8         filter_index[0x10];
10423 
10424 	u8         reserved_1[0x20];
10425 
10426 	u8         filter_val[0x20];
10427 
10428 	u8         reserved_2[0x1a0];
10429 };
10430 
10431 struct mlx5_ifc_trc_event_reg_bits {
10432 	u8         status[0x1];
10433 	u8         reserved_0[0xf];
10434 	u8         event_index[0x10];
10435 
10436 	u8         reserved_1[0x20];
10437 
10438 	u8         event_id[0x20];
10439 
10440 	u8         event_selector_val[0x10];
10441 	u8         event_selector_size[0x10];
10442 
10443 	u8         reserved_2[0x180];
10444 };
10445 
10446 struct mlx5_ifc_trc_conf_reg_bits {
10447 	u8         limit_en[0x1];
10448 	u8         reserved_0[0x3];
10449 	u8         dump_mode[0x4];
10450 	u8         reserved_1[0x15];
10451 	u8         state[0x3];
10452 
10453 	u8         reserved_2[0x20];
10454 
10455 	u8         limit_event_index[0x20];
10456 
10457 	u8         mkey[0x20];
10458 
10459 	u8         fifo_ready_ev_num[0x20];
10460 
10461 	u8         reserved_3[0x160];
10462 };
10463 
10464 struct mlx5_ifc_trc_cap_reg_bits {
10465 	u8         reserved_0[0x18];
10466 	u8         dump_mode[0x8];
10467 
10468 	u8         reserved_1[0x20];
10469 
10470 	u8         num_of_events[0x10];
10471 	u8         num_of_filters[0x10];
10472 
10473 	u8         fifo_size[0x20];
10474 
10475 	u8         tlb_size[0x10];
10476 	u8         event_size[0x10];
10477 
10478 	u8         reserved_2[0x160];
10479 };
10480 
10481 struct mlx5_ifc_set_node_in_bits {
10482 	u8         node_description[64][0x8];
10483 };
10484 
10485 struct mlx5_ifc_register_power_settings_bits {
10486 	u8         reserved_0[0x18];
10487 	u8         power_settings_level[0x8];
10488 
10489 	u8         reserved_1[0x60];
10490 };
10491 
10492 struct mlx5_ifc_register_host_endianess_bits {
10493 	u8         he[0x1];
10494 	u8         reserved_0[0x1f];
10495 
10496 	u8         reserved_1[0x60];
10497 };
10498 
10499 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
10500 	u8         physical_address[0x40];
10501 };
10502 
10503 struct mlx5_ifc_qtct_reg_bits {
10504 	u8         operation_type[0x2];
10505 	u8         cap_local_admin[0x1];
10506 	u8         cap_remote_admin[0x1];
10507 	u8         reserved_0[0x4];
10508 	u8         port_number[0x8];
10509 	u8         reserved_1[0xd];
10510 	u8         prio[0x3];
10511 
10512 	u8         reserved_2[0x1d];
10513 	u8         tclass[0x3];
10514 };
10515 
10516 struct mlx5_ifc_qpdp_reg_bits {
10517 	u8         reserved_0[0x8];
10518 	u8         port_number[0x8];
10519 	u8         reserved_1[0x10];
10520 
10521 	u8         reserved_2[0x1d];
10522 	u8         pprio[0x3];
10523 };
10524 
10525 struct mlx5_ifc_port_info_ro_fields_param_bits {
10526 	u8         reserved_0[0x8];
10527 	u8         port[0x8];
10528 	u8         max_gid[0x10];
10529 
10530 	u8         reserved_1[0x20];
10531 
10532 	u8         port_guid[0x40];
10533 };
10534 
10535 struct mlx5_ifc_nvqc_reg_bits {
10536 	u8         type[0x20];
10537 
10538 	u8         reserved_0[0x18];
10539 	u8         version[0x4];
10540 	u8         reserved_1[0x2];
10541 	u8         support_wr[0x1];
10542 	u8         support_rd[0x1];
10543 };
10544 
10545 struct mlx5_ifc_nvia_reg_bits {
10546 	u8         reserved_0[0x1d];
10547 	u8         target[0x3];
10548 
10549 	u8         reserved_1[0x20];
10550 };
10551 
10552 struct mlx5_ifc_nvdi_reg_bits {
10553 	struct mlx5_ifc_config_item_bits configuration_item_header;
10554 };
10555 
10556 struct mlx5_ifc_nvda_reg_bits {
10557 	struct mlx5_ifc_config_item_bits configuration_item_header;
10558 
10559 	u8         configuration_item_data[0x20];
10560 };
10561 
10562 struct mlx5_ifc_node_info_ro_fields_param_bits {
10563 	u8         system_image_guid[0x40];
10564 
10565 	u8         reserved_0[0x40];
10566 
10567 	u8         node_guid[0x40];
10568 
10569 	u8         reserved_1[0x10];
10570 	u8         max_pkey[0x10];
10571 
10572 	u8         reserved_2[0x20];
10573 };
10574 
10575 struct mlx5_ifc_ets_tcn_config_reg_bits {
10576 	u8         g[0x1];
10577 	u8         b[0x1];
10578 	u8         r[0x1];
10579 	u8         reserved_0[0x9];
10580 	u8         group[0x4];
10581 	u8         reserved_1[0x9];
10582 	u8         bw_allocation[0x7];
10583 
10584 	u8         reserved_2[0xc];
10585 	u8         max_bw_units[0x4];
10586 	u8         reserved_3[0x8];
10587 	u8         max_bw_value[0x8];
10588 };
10589 
10590 struct mlx5_ifc_ets_global_config_reg_bits {
10591 	u8         reserved_0[0x2];
10592 	u8         r[0x1];
10593 	u8         reserved_1[0x1d];
10594 
10595 	u8         reserved_2[0xc];
10596 	u8         max_bw_units[0x4];
10597 	u8         reserved_3[0x8];
10598 	u8         max_bw_value[0x8];
10599 };
10600 
10601 struct mlx5_ifc_qetc_reg_bits {
10602 	u8                                         reserved_at_0[0x8];
10603 	u8                                         port_number[0x8];
10604 	u8                                         reserved_at_10[0x30];
10605 
10606 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10607 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10608 };
10609 
10610 struct mlx5_ifc_nodnic_mac_filters_bits {
10611 	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
10612 
10613 	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
10614 
10615 	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
10616 
10617 	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
10618 
10619 	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
10620 
10621 	u8         reserved_0[0xc0];
10622 };
10623 
10624 struct mlx5_ifc_nodnic_gid_filters_bits {
10625 	u8         mgid_filter0[16][0x8];
10626 
10627 	u8         mgid_filter1[16][0x8];
10628 
10629 	u8         mgid_filter2[16][0x8];
10630 
10631 	u8         mgid_filter3[16][0x8];
10632 };
10633 
10634 enum {
10635 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
10636 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
10637 };
10638 
10639 enum {
10640 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
10641 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
10642 };
10643 
10644 struct mlx5_ifc_nodnic_config_reg_bits {
10645 	u8         no_dram_nic_revision[0x8];
10646 	u8         hardware_format[0x8];
10647 	u8         support_receive_filter[0x1];
10648 	u8         support_promisc_filter[0x1];
10649 	u8         support_promisc_multicast_filter[0x1];
10650 	u8         reserved_0[0x2];
10651 	u8         log_working_buffer_size[0x3];
10652 	u8         log_pkey_table_size[0x4];
10653 	u8         reserved_1[0x3];
10654 	u8         num_ports[0x1];
10655 
10656 	u8         reserved_2[0x2];
10657 	u8         log_max_ring_size[0x6];
10658 	u8         reserved_3[0x18];
10659 
10660 	u8         lkey[0x20];
10661 
10662 	u8         cqe_format[0x4];
10663 	u8         reserved_4[0x1c];
10664 
10665 	u8         node_guid[0x40];
10666 
10667 	u8         reserved_5[0x740];
10668 
10669 	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
10670 
10671 	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
10672 };
10673 
10674 struct mlx5_ifc_vlan_layout_bits {
10675 	u8         reserved_0[0x14];
10676 	u8         vlan[0xc];
10677 
10678 	u8         reserved_1[0x20];
10679 };
10680 
10681 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10682 	u8         reserved_0[0x20];
10683 
10684 	u8         mkey[0x20];
10685 
10686 	u8         addressh_63_32[0x20];
10687 
10688 	u8         addressl_31_0[0x20];
10689 };
10690 
10691 struct mlx5_ifc_ud_adrs_vector_bits {
10692 	u8         dc_key[0x40];
10693 
10694 	u8         ext[0x1];
10695 	u8         reserved_0[0x7];
10696 	u8         destination_qp_dct[0x18];
10697 
10698 	u8         static_rate[0x4];
10699 	u8         sl_eth_prio[0x4];
10700 	u8         fl[0x1];
10701 	u8         mlid[0x7];
10702 	u8         rlid_udp_sport[0x10];
10703 
10704 	u8         reserved_1[0x20];
10705 
10706 	u8         rmac_47_16[0x20];
10707 
10708 	u8         rmac_15_0[0x10];
10709 	u8         tclass[0x8];
10710 	u8         hop_limit[0x8];
10711 
10712 	u8         reserved_2[0x1];
10713 	u8         grh[0x1];
10714 	u8         reserved_3[0x2];
10715 	u8         src_addr_index[0x8];
10716 	u8         flow_label[0x14];
10717 
10718 	u8         rgid_rip[16][0x8];
10719 };
10720 
10721 struct mlx5_ifc_port_module_event_bits {
10722 	u8         reserved_0[0x8];
10723 	u8         module[0x8];
10724 	u8         reserved_1[0xc];
10725 	u8         module_status[0x4];
10726 
10727 	u8         reserved_2[0x14];
10728 	u8         error_type[0x4];
10729 	u8         reserved_3[0x8];
10730 
10731 	u8         reserved_4[0xa0];
10732 };
10733 
10734 struct mlx5_ifc_icmd_control_bits {
10735 	u8         opcode[0x10];
10736 	u8         status[0x8];
10737 	u8         reserved_0[0x7];
10738 	u8         busy[0x1];
10739 };
10740 
10741 struct mlx5_ifc_eqe_bits {
10742 	u8         reserved_0[0x8];
10743 	u8         event_type[0x8];
10744 	u8         reserved_1[0x8];
10745 	u8         event_sub_type[0x8];
10746 
10747 	u8         reserved_2[0xe0];
10748 
10749 	union mlx5_ifc_event_auto_bits event_data;
10750 
10751 	u8         reserved_3[0x10];
10752 	u8         signature[0x8];
10753 	u8         reserved_4[0x7];
10754 	u8         owner[0x1];
10755 };
10756 
10757 enum {
10758 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10759 };
10760 
10761 struct mlx5_ifc_cmd_queue_entry_bits {
10762 	u8         type[0x8];
10763 	u8         reserved_0[0x18];
10764 
10765 	u8         input_length[0x20];
10766 
10767 	u8         input_mailbox_pointer_63_32[0x20];
10768 
10769 	u8         input_mailbox_pointer_31_9[0x17];
10770 	u8         reserved_1[0x9];
10771 
10772 	u8         command_input_inline_data[16][0x8];
10773 
10774 	u8         command_output_inline_data[16][0x8];
10775 
10776 	u8         output_mailbox_pointer_63_32[0x20];
10777 
10778 	u8         output_mailbox_pointer_31_9[0x17];
10779 	u8         reserved_2[0x9];
10780 
10781 	u8         output_length[0x20];
10782 
10783 	u8         token[0x8];
10784 	u8         signature[0x8];
10785 	u8         reserved_3[0x8];
10786 	u8         status[0x7];
10787 	u8         ownership[0x1];
10788 };
10789 
10790 struct mlx5_ifc_cmd_out_bits {
10791 	u8         status[0x8];
10792 	u8         reserved_0[0x18];
10793 
10794 	u8         syndrome[0x20];
10795 
10796 	u8         command_output[0x20];
10797 };
10798 
10799 struct mlx5_ifc_cmd_in_bits {
10800 	u8         opcode[0x10];
10801 	u8         reserved_0[0x10];
10802 
10803 	u8         reserved_1[0x10];
10804 	u8         op_mod[0x10];
10805 
10806 	u8         command[0][0x20];
10807 };
10808 
10809 struct mlx5_ifc_cmd_if_box_bits {
10810 	u8         mailbox_data[512][0x8];
10811 
10812 	u8         reserved_0[0x180];
10813 
10814 	u8         next_pointer_63_32[0x20];
10815 
10816 	u8         next_pointer_31_10[0x16];
10817 	u8         reserved_1[0xa];
10818 
10819 	u8         block_number[0x20];
10820 
10821 	u8         reserved_2[0x8];
10822 	u8         token[0x8];
10823 	u8         ctrl_signature[0x8];
10824 	u8         signature[0x8];
10825 };
10826 
10827 struct mlx5_ifc_mtt_bits {
10828 	u8         ptag_63_32[0x20];
10829 
10830 	u8         ptag_31_8[0x18];
10831 	u8         reserved_0[0x6];
10832 	u8         wr_en[0x1];
10833 	u8         rd_en[0x1];
10834 };
10835 
10836 struct mlx5_ifc_tls_progress_params_bits {
10837 	u8         valid[0x1];
10838 	u8         reserved_at_1[0x7];
10839 	u8         pd[0x18];
10840 
10841 	u8         next_record_tcp_sn[0x20];
10842 
10843 	u8         hw_resync_tcp_sn[0x20];
10844 
10845 	u8         record_tracker_state[0x2];
10846 	u8         auth_state[0x2];
10847 	u8         reserved_at_64[0x4];
10848 	u8         hw_offset_record_number[0x18];
10849 };
10850 
10851 struct mlx5_ifc_tls_static_params_bits {
10852 	u8         const_2[0x2];
10853 	u8         tls_version[0x4];
10854 	u8         const_1[0x2];
10855 	u8         reserved_at_8[0x14];
10856 	u8         encryption_standard[0x4];
10857 
10858 	u8         reserved_at_20[0x20];
10859 
10860 	u8         initial_record_number[0x40];
10861 
10862 	u8         resync_tcp_sn[0x20];
10863 
10864 	u8         gcm_iv[0x20];
10865 
10866 	u8         implicit_iv[0x40];
10867 
10868 	u8         reserved_at_100[0x8];
10869 	u8         dek_index[0x18];
10870 
10871 	u8         reserved_at_120[0xe0];
10872 };
10873 
10874 /* Vendor Specific Capabilities, VSC */
10875 enum {
10876 	MLX5_VSC_DOMAIN_ICMD			= 0x1,
10877 	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
10878 	MLX5_VSC_DOMAIN_SCAN_CRSPACE		= 0x7,
10879 	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
10880 };
10881 
10882 struct mlx5_ifc_vendor_specific_cap_bits {
10883 	u8         type[0x8];
10884 	u8         length[0x8];
10885 	u8         next_pointer[0x8];
10886 	u8         capability_id[0x8];
10887 
10888 	u8         status[0x3];
10889 	u8         reserved_0[0xd];
10890 	u8         space[0x10];
10891 
10892 	u8         counter[0x20];
10893 
10894 	u8         semaphore[0x20];
10895 
10896 	u8         flag[0x1];
10897 	u8         reserved_1[0x1];
10898 	u8         address[0x1e];
10899 
10900 	u8         data[0x20];
10901 };
10902 
10903 struct mlx5_ifc_vsc_space_bits {
10904 	u8 status[0x3];
10905 	u8 reserved0[0xd];
10906 	u8 space[0x10];
10907 };
10908 
10909 struct mlx5_ifc_vsc_addr_bits {
10910 	u8 flag[0x1];
10911 	u8 reserved0[0x1];
10912 	u8 address[0x1e];
10913 };
10914 
10915 enum {
10916 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10917 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10918 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10919 };
10920 
10921 enum {
10922 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10923 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10924 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10925 };
10926 
10927 enum {
10928 	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
10929 	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
10930 	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
10931 	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
10932 	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
10933 	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
10934 	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
10935 	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
10936 	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
10937 	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
10938 	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
10939 };
10940 
10941 struct mlx5_ifc_initial_seg_bits {
10942 	u8         fw_rev_minor[0x10];
10943 	u8         fw_rev_major[0x10];
10944 
10945 	u8         cmd_interface_rev[0x10];
10946 	u8         fw_rev_subminor[0x10];
10947 
10948 	u8         reserved_0[0x40];
10949 
10950 	u8         cmdq_phy_addr_63_32[0x20];
10951 
10952 	u8         cmdq_phy_addr_31_12[0x14];
10953 	u8         reserved_1[0x2];
10954 	u8         nic_interface[0x2];
10955 	u8         log_cmdq_size[0x4];
10956 	u8         log_cmdq_stride[0x4];
10957 
10958 	u8         command_doorbell_vector[0x20];
10959 
10960 	u8         reserved_2[0xf00];
10961 
10962 	u8         initializing[0x1];
10963 	u8         reserved_3[0x4];
10964 	u8         nic_interface_supported[0x3];
10965 	u8         reserved_4[0x18];
10966 
10967 	struct mlx5_ifc_health_buffer_bits health_buffer;
10968 
10969 	u8         no_dram_nic_offset[0x20];
10970 
10971 	u8         reserved_5[0x6de0];
10972 
10973 	u8         internal_timer_h[0x20];
10974 
10975 	u8         internal_timer_l[0x20];
10976 
10977 	u8         reserved_6[0x20];
10978 
10979 	u8         reserved_7[0x1f];
10980 	u8         clear_int[0x1];
10981 
10982 	u8         health_syndrome[0x8];
10983 	u8         health_counter[0x18];
10984 
10985 	u8         reserved_8[0x17fc0];
10986 };
10987 
10988 union mlx5_ifc_icmd_interface_document_bits {
10989 	struct mlx5_ifc_fw_version_bits fw_version;
10990 	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10991 	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10992 	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10993 	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10994 	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10995 	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10996 	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10997 	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10998 	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10999 	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
11000 	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
11001 	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
11002 	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
11003 	u8         reserved_0[0x42c0];
11004 };
11005 
11006 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
11007 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11008 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11009 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11010 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11011 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11012 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
11013 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11014 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11015 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
11016 	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
11017 	u8         reserved_0[0x7c0];
11018 };
11019 
11020 struct mlx5_ifc_ppcnt_reg_bits {
11021 	u8         swid[0x8];
11022 	u8         local_port[0x8];
11023 	u8         pnat[0x2];
11024 	u8         reserved_0[0x8];
11025 	u8         grp[0x6];
11026 
11027 	u8         clr[0x1];
11028 	u8         reserved_1[0x1c];
11029 	u8         prio_tc[0x3];
11030 
11031 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
11032 };
11033 
11034 struct mlx5_ifc_pcie_lanes_counters_bits {
11035 	u8         life_time_counter_high[0x20];
11036 
11037 	u8         life_time_counter_low[0x20];
11038 
11039 	u8         error_counter_lane0[0x20];
11040 
11041 	u8         error_counter_lane1[0x20];
11042 
11043 	u8         error_counter_lane2[0x20];
11044 
11045 	u8         error_counter_lane3[0x20];
11046 
11047 	u8         error_counter_lane4[0x20];
11048 
11049 	u8         error_counter_lane5[0x20];
11050 
11051 	u8         error_counter_lane6[0x20];
11052 
11053 	u8         error_counter_lane7[0x20];
11054 
11055 	u8         error_counter_lane8[0x20];
11056 
11057 	u8         error_counter_lane9[0x20];
11058 
11059 	u8         error_counter_lane10[0x20];
11060 
11061 	u8         error_counter_lane11[0x20];
11062 
11063 	u8         error_counter_lane12[0x20];
11064 
11065 	u8         error_counter_lane13[0x20];
11066 
11067 	u8         error_counter_lane14[0x20];
11068 
11069 	u8         error_counter_lane15[0x20];
11070 
11071 	u8         reserved_at_240[0x580];
11072 };
11073 
11074 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
11075 	u8         reserved_at_0[0x40];
11076 
11077 	u8         error_counter_lane0[0x20];
11078 
11079 	u8         error_counter_lane1[0x20];
11080 
11081 	u8         error_counter_lane2[0x20];
11082 
11083 	u8         error_counter_lane3[0x20];
11084 
11085 	u8         error_counter_lane4[0x20];
11086 
11087 	u8         error_counter_lane5[0x20];
11088 
11089 	u8         error_counter_lane6[0x20];
11090 
11091 	u8         error_counter_lane7[0x20];
11092 
11093 	u8         error_counter_lane8[0x20];
11094 
11095 	u8         error_counter_lane9[0x20];
11096 
11097 	u8         error_counter_lane10[0x20];
11098 
11099 	u8         error_counter_lane11[0x20];
11100 
11101 	u8         error_counter_lane12[0x20];
11102 
11103 	u8         error_counter_lane13[0x20];
11104 
11105 	u8         error_counter_lane14[0x20];
11106 
11107 	u8         error_counter_lane15[0x20];
11108 
11109 	u8         reserved_at_240[0x580];
11110 };
11111 
11112 struct mlx5_ifc_pcie_perf_counters_bits {
11113 	u8         life_time_counter_high[0x20];
11114 
11115 	u8         life_time_counter_low[0x20];
11116 
11117 	u8         rx_errors[0x20];
11118 
11119 	u8         tx_errors[0x20];
11120 
11121 	u8         l0_to_recovery_eieos[0x20];
11122 
11123 	u8         l0_to_recovery_ts[0x20];
11124 
11125 	u8         l0_to_recovery_framing[0x20];
11126 
11127 	u8         l0_to_recovery_retrain[0x20];
11128 
11129 	u8         crc_error_dllp[0x20];
11130 
11131 	u8         crc_error_tlp[0x20];
11132 
11133 	u8         tx_overflow_buffer_pkt[0x40];
11134 
11135 	u8         outbound_stalled_reads[0x20];
11136 
11137 	u8         outbound_stalled_writes[0x20];
11138 
11139 	u8         outbound_stalled_reads_events[0x20];
11140 
11141 	u8         outbound_stalled_writes_events[0x20];
11142 
11143 	u8         tx_overflow_buffer_marked_pkt[0x40];
11144 
11145 	u8         reserved_at_240[0x580];
11146 };
11147 
11148 struct mlx5_ifc_pcie_perf_counters_ext_bits {
11149 	u8         reserved_at_0[0x40];
11150 
11151 	u8         rx_errors[0x20];
11152 
11153 	u8         tx_errors[0x20];
11154 
11155 	u8         reserved_at_80[0xc0];
11156 
11157 	u8         tx_overflow_buffer_pkt[0x40];
11158 
11159 	u8         outbound_stalled_reads[0x20];
11160 
11161 	u8         outbound_stalled_writes[0x20];
11162 
11163 	u8         outbound_stalled_reads_events[0x20];
11164 
11165 	u8         outbound_stalled_writes_events[0x20];
11166 
11167 	u8         tx_overflow_buffer_marked_pkt[0x40];
11168 
11169 	u8         reserved_at_240[0x580];
11170 };
11171 
11172 struct mlx5_ifc_pcie_timers_states_bits {
11173 	u8         life_time_counter_high[0x20];
11174 
11175 	u8         life_time_counter_low[0x20];
11176 
11177 	u8         time_to_boot_image_start[0x20];
11178 
11179 	u8         time_to_link_image[0x20];
11180 
11181 	u8         calibration_time[0x20];
11182 
11183 	u8         time_to_first_perst[0x20];
11184 
11185 	u8         time_to_detect_state[0x20];
11186 
11187 	u8         time_to_l0[0x20];
11188 
11189 	u8         time_to_crs_en[0x20];
11190 
11191 	u8         time_to_plastic_image_start[0x20];
11192 
11193 	u8         time_to_iron_image_start[0x20];
11194 
11195 	u8         perst_handler[0x20];
11196 
11197 	u8         times_in_l1[0x20];
11198 
11199 	u8         times_in_l23[0x20];
11200 
11201 	u8         dl_down[0x20];
11202 
11203 	u8         config_cycle1usec[0x20];
11204 
11205 	u8         config_cycle2to7usec[0x20];
11206 
11207 	u8         config_cycle8to15usec[0x20];
11208 
11209 	u8         config_cycle16to63usec[0x20];
11210 
11211 	u8         config_cycle64usec[0x20];
11212 
11213 	u8         correctable_err_msg_sent[0x20];
11214 
11215 	u8         non_fatal_err_msg_sent[0x20];
11216 
11217 	u8         fatal_err_msg_sent[0x20];
11218 
11219 	u8         reserved_at_2e0[0x4e0];
11220 };
11221 
11222 struct mlx5_ifc_pcie_timers_states_ext_bits {
11223 	u8         reserved_at_0[0x40];
11224 
11225 	u8         time_to_boot_image_start[0x20];
11226 
11227 	u8         time_to_link_image[0x20];
11228 
11229 	u8         calibration_time[0x20];
11230 
11231 	u8         time_to_first_perst[0x20];
11232 
11233 	u8         time_to_detect_state[0x20];
11234 
11235 	u8         time_to_l0[0x20];
11236 
11237 	u8         time_to_crs_en[0x20];
11238 
11239 	u8         time_to_plastic_image_start[0x20];
11240 
11241 	u8         time_to_iron_image_start[0x20];
11242 
11243 	u8         perst_handler[0x20];
11244 
11245 	u8         times_in_l1[0x20];
11246 
11247 	u8         times_in_l23[0x20];
11248 
11249 	u8         dl_down[0x20];
11250 
11251 	u8         config_cycle1usec[0x20];
11252 
11253 	u8         config_cycle2to7usec[0x20];
11254 
11255 	u8         config_cycle8to15usec[0x20];
11256 
11257 	u8         config_cycle16to63usec[0x20];
11258 
11259 	u8         config_cycle64usec[0x20];
11260 
11261 	u8         correctable_err_msg_sent[0x20];
11262 
11263 	u8         non_fatal_err_msg_sent[0x20];
11264 
11265 	u8         fatal_err_msg_sent[0x20];
11266 
11267 	u8         reserved_at_2e0[0x4e0];
11268 };
11269 
11270 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
11271 	struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
11272 	struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
11273 	struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
11274 	u8         reserved_at_0[0x7c0];
11275 };
11276 
11277 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
11278 	struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
11279 	struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
11280 	struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
11281 	u8         reserved_at_0[0x7c0];
11282 };
11283 
11284 struct mlx5_ifc_mpcnt_reg_bits {
11285 	u8         reserved_at_0[0x2];
11286 	u8         depth[0x6];
11287 	u8         pcie_index[0x8];
11288 	u8         node[0x8];
11289 	u8         reserved_at_18[0x2];
11290 	u8         grp[0x6];
11291 
11292 	u8         clr[0x1];
11293 	u8         reserved_at_21[0x1f];
11294 
11295 	union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
11296 };
11297 
11298 struct mlx5_ifc_mpcnt_reg_ext_bits {
11299 	u8         reserved_at_0[0x2];
11300 	u8         depth[0x6];
11301 	u8         pcie_index[0x8];
11302 	u8         node[0x8];
11303 	u8         reserved_at_18[0x2];
11304 	u8         grp[0x6];
11305 
11306 	u8         clr[0x1];
11307 	u8         reserved_at_21[0x1f];
11308 
11309 	union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
11310 };
11311 
11312 struct mlx5_ifc_monitor_opcodes_layout_bits {
11313 	u8         reserved_at_0[0x10];
11314 	u8         monitor_opcode[0x10];
11315 };
11316 
11317 union mlx5_ifc_pddr_status_opcode_bits {
11318 	struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
11319 	u8         reserved_at_0[0x20];
11320 };
11321 
11322 struct mlx5_ifc_troubleshooting_info_page_layout_bits {
11323 	u8         reserved_at_0[0x10];
11324 	u8         group_opcode[0x10];
11325 
11326 	union mlx5_ifc_pddr_status_opcode_bits status_opcode;
11327 
11328 	u8         user_feedback_data[0x10];
11329 	u8         user_feedback_index[0x10];
11330 
11331 	u8         status_message[0x760];
11332 };
11333 
11334 union mlx5_ifc_pddr_page_data_bits {
11335 	struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
11336 	struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
11337 	u8         reserved_at_0[0x7c0];
11338 };
11339 
11340 struct mlx5_ifc_pddr_reg_bits {
11341 	u8         reserved_at_0[0x8];
11342 	u8         local_port[0x8];
11343 	u8         pnat[0x2];
11344 	u8         reserved_at_12[0xe];
11345 
11346 	u8         reserved_at_20[0x18];
11347 	u8         page_select[0x8];
11348 
11349 	union mlx5_ifc_pddr_page_data_bits page_data;
11350 };
11351 
11352 enum {
11353 	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
11354 	MLX5_MPEIN_PWR_STATUS_INVALID = 0,
11355 	MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
11356 	MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
11357 };
11358 
11359 struct mlx5_ifc_mpein_reg_bits {
11360 	u8         reserved_at_0[0x2];
11361 	u8         depth[0x6];
11362 	u8         pcie_index[0x8];
11363 	u8         node[0x8];
11364 	u8         reserved_at_18[0x8];
11365 
11366 	u8         capability_mask[0x20];
11367 
11368 	u8         reserved_at_40[0x8];
11369 	u8         link_width_enabled[0x8];
11370 	u8         link_speed_enabled[0x10];
11371 
11372 	u8         lane0_physical_position[0x8];
11373 	u8         link_width_active[0x8];
11374 	u8         link_speed_active[0x10];
11375 
11376 	u8         num_of_pfs[0x10];
11377 	u8         num_of_vfs[0x10];
11378 
11379 	u8         bdf0[0x10];
11380 	u8         reserved_at_b0[0x10];
11381 
11382 	u8         max_read_request_size[0x4];
11383 	u8         max_payload_size[0x4];
11384 	u8         reserved_at_c8[0x5];
11385 	u8         pwr_status[0x3];
11386 	u8         port_type[0x4];
11387 	u8         reserved_at_d4[0xb];
11388 	u8         lane_reversal[0x1];
11389 
11390 	u8         reserved_at_e0[0x14];
11391 	u8         pci_power[0xc];
11392 
11393 	u8         reserved_at_100[0x20];
11394 
11395 	u8         device_status[0x10];
11396 	u8         port_state[0x8];
11397 	u8         reserved_at_138[0x8];
11398 
11399 	u8         reserved_at_140[0x10];
11400 	u8         receiver_detect_result[0x10];
11401 
11402 	u8         reserved_at_160[0x20];
11403 };
11404 
11405 struct mlx5_ifc_mpein_reg_ext_bits {
11406 	u8         reserved_at_0[0x2];
11407 	u8         depth[0x6];
11408 	u8         pcie_index[0x8];
11409 	u8         node[0x8];
11410 	u8         reserved_at_18[0x8];
11411 
11412 	u8         reserved_at_20[0x20];
11413 
11414 	u8         reserved_at_40[0x8];
11415 	u8         link_width_enabled[0x8];
11416 	u8         link_speed_enabled[0x10];
11417 
11418 	u8         lane0_physical_position[0x8];
11419 	u8         link_width_active[0x8];
11420 	u8         link_speed_active[0x10];
11421 
11422 	u8         num_of_pfs[0x10];
11423 	u8         num_of_vfs[0x10];
11424 
11425 	u8         bdf0[0x10];
11426 	u8         reserved_at_b0[0x10];
11427 
11428 	u8         max_read_request_size[0x4];
11429 	u8         max_payload_size[0x4];
11430 	u8         reserved_at_c8[0x5];
11431 	u8         pwr_status[0x3];
11432 	u8         port_type[0x4];
11433 	u8         reserved_at_d4[0xb];
11434 	u8         lane_reversal[0x1];
11435 };
11436 
11437 struct mlx5_ifc_mcqi_cap_bits {
11438 	u8         supported_info_bitmask[0x20];
11439 
11440 	u8         component_size[0x20];
11441 
11442 	u8         max_component_size[0x20];
11443 
11444 	u8         log_mcda_word_size[0x4];
11445 	u8         reserved_at_64[0xc];
11446 	u8         mcda_max_write_size[0x10];
11447 
11448 	u8         rd_en[0x1];
11449 	u8         reserved_at_81[0x1];
11450 	u8         match_chip_id[0x1];
11451 	u8         match_psid[0x1];
11452 	u8         check_user_timestamp[0x1];
11453 	u8         match_base_guid_mac[0x1];
11454 	u8         reserved_at_86[0x1a];
11455 };
11456 
11457 struct mlx5_ifc_mcqi_reg_bits {
11458 	u8         read_pending_component[0x1];
11459 	u8         reserved_at_1[0xf];
11460 	u8         component_index[0x10];
11461 
11462 	u8         reserved_at_20[0x20];
11463 
11464 	u8         reserved_at_40[0x1b];
11465 	u8         info_type[0x5];
11466 
11467 	u8         info_size[0x20];
11468 
11469 	u8         offset[0x20];
11470 
11471 	u8         reserved_at_a0[0x10];
11472 	u8         data_size[0x10];
11473 
11474 	u8         data[0][0x20];
11475 };
11476 
11477 struct mlx5_ifc_mcc_reg_bits {
11478 	u8         reserved_at_0[0x4];
11479 	u8         time_elapsed_since_last_cmd[0xc];
11480 	u8         reserved_at_10[0x8];
11481 	u8         instruction[0x8];
11482 
11483 	u8         reserved_at_20[0x10];
11484 	u8         component_index[0x10];
11485 
11486 	u8         reserved_at_40[0x8];
11487 	u8         update_handle[0x18];
11488 
11489 	u8         handle_owner_type[0x4];
11490 	u8         handle_owner_host_id[0x4];
11491 	u8         reserved_at_68[0x1];
11492 	u8         control_progress[0x7];
11493 	u8         error_code[0x8];
11494 	u8         reserved_at_78[0x4];
11495 	u8         control_state[0x4];
11496 
11497 	u8         component_size[0x20];
11498 
11499 	u8         reserved_at_a0[0x60];
11500 };
11501 
11502 struct mlx5_ifc_mcda_reg_bits {
11503 	u8         reserved_at_0[0x8];
11504 	u8         update_handle[0x18];
11505 
11506 	u8         offset[0x20];
11507 
11508 	u8         reserved_at_40[0x10];
11509 	u8         size[0x10];
11510 
11511 	u8         reserved_at_60[0x20];
11512 
11513 	u8         data[0][0x20];
11514 };
11515 
11516 union mlx5_ifc_ports_control_registers_document_bits {
11517 	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
11518 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11519 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11520 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11521 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11522 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11523 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
11524 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11525 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11526 	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
11527 	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
11528 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11529 	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
11530 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11531 	struct mlx5_ifc_paos_reg_bits paos_reg;
11532 	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
11533 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11534 	struct mlx5_ifc_peir_reg_bits peir_reg;
11535 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11536 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11537 	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
11538 	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
11539 	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
11540 	struct mlx5_ifc_phrr_reg_bits phrr_reg;
11541 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11542 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11543 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11544 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11545 	struct mlx5_ifc_plib_reg_bits plib_reg;
11546 	struct mlx5_ifc_pll_status_data_bits pll_status_data;
11547 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11548 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11549 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11550 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11551 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11552 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11553 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11554 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11555 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11556 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11557 	struct mlx5_ifc_ppll_reg_bits ppll_reg;
11558 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11559 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11560 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11561 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11562 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11563 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11564 	struct mlx5_ifc_pude_reg_bits pude_reg;
11565 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11566 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11567 	struct mlx5_ifc_slrp_reg_bits slrp_reg;
11568 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11569 	u8         reserved_0[0x7880];
11570 };
11571 
11572 union mlx5_ifc_debug_enhancements_document_bits {
11573 	struct mlx5_ifc_health_buffer_bits health_buffer;
11574 	u8         reserved_0[0x200];
11575 };
11576 
11577 union mlx5_ifc_no_dram_nic_document_bits {
11578 	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
11579 	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
11580 	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
11581 	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
11582 	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
11583 	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
11584 	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
11585 	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
11586 	u8         reserved_0[0x3160];
11587 };
11588 
11589 union mlx5_ifc_uplink_pci_interface_document_bits {
11590 	struct mlx5_ifc_initial_seg_bits initial_seg;
11591 	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
11592 	u8         reserved_0[0x20120];
11593 };
11594 
11595 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11596 	u8         e[0x1];
11597 	u8         reserved_at_01[0x0b];
11598 	u8         prio[0x04];
11599 };
11600 
11601 struct mlx5_ifc_qpdpm_reg_bits {
11602 	u8                                     reserved_at_0[0x8];
11603 	u8                                     local_port[0x8];
11604 	u8                                     reserved_at_10[0x10];
11605 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11606 };
11607 
11608 struct mlx5_ifc_qpts_reg_bits {
11609 	u8         reserved_at_0[0x8];
11610 	u8         local_port[0x8];
11611 	u8         reserved_at_10[0x2d];
11612 	u8         trust_state[0x3];
11613 };
11614 
11615 struct mlx5_ifc_mfrl_reg_bits {
11616 	u8         reserved_at_0[0x38];
11617 	u8         reset_level[0x8];
11618 };
11619 
11620 enum {
11621       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP	= 0x9009,
11622       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR	= 0x9109,
11623       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP	= 0x900a,
11624       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE	= 0x900b,
11625       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR	= 0x900f,
11626       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE	= 0x910b,
11627       MLX5_MAX_TEMPERATURE = 16,
11628 };
11629 
11630 struct mlx5_ifc_mtbr_temp_record_bits {
11631 	u8         max_temperature[0x10];
11632 	u8         temperature[0x10];
11633 };
11634 
11635 struct mlx5_ifc_mtbr_reg_bits {
11636 	u8         reserved_at_0[0x14];
11637 	u8         base_sensor_index[0xc];
11638 
11639 	u8         reserved_at_20[0x18];
11640 	u8         num_rec[0x8];
11641 
11642 	u8         reserved_at_40[0x40];
11643 
11644 	struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11645 };
11646 
11647 struct mlx5_ifc_mtbr_reg_ext_bits {
11648 	u8         reserved_at_0[0x14];
11649 	u8         base_sensor_index[0xc];
11650 
11651 	u8         reserved_at_20[0x18];
11652 	u8         num_rec[0x8];
11653 
11654 	u8         reserved_at_40[0x40];
11655 
11656     struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11657 };
11658 
11659 struct mlx5_ifc_mtcap_bits {
11660 	u8         reserved_at_0[0x19];
11661 	u8         sensor_count[0x7];
11662 
11663 	u8         reserved_at_20[0x19];
11664 	u8         internal_sensor_count[0x7];
11665 
11666 	u8         sensor_map[0x40];
11667 };
11668 
11669 struct mlx5_ifc_mtcap_ext_bits {
11670 	u8         reserved_at_0[0x19];
11671 	u8         sensor_count[0x7];
11672 
11673 	u8         reserved_at_20[0x20];
11674 
11675 	u8         sensor_map[0x40];
11676 };
11677 
11678 struct mlx5_ifc_mtecr_bits {
11679 	u8         reserved_at_0[0x4];
11680 	u8         last_sensor[0xc];
11681 	u8         reserved_at_10[0x4];
11682 	u8         sensor_count[0xc];
11683 
11684 	u8         reserved_at_20[0x19];
11685 	u8         internal_sensor_count[0x7];
11686 
11687 	u8         sensor_map_0[0x20];
11688 
11689 	u8         reserved_at_60[0x2a0];
11690 };
11691 
11692 struct mlx5_ifc_mtecr_ext_bits {
11693 	u8         reserved_at_0[0x4];
11694 	u8         last_sensor[0xc];
11695 	u8         reserved_at_10[0x4];
11696 	u8         sensor_count[0xc];
11697 
11698 	u8         reserved_at_20[0x20];
11699 
11700 	u8         sensor_map_0[0x20];
11701 
11702 	u8         reserved_at_60[0x2a0];
11703 };
11704 
11705 struct mlx5_ifc_mtewe_bits {
11706 	u8         reserved_at_0[0x4];
11707 	u8         last_sensor[0xc];
11708 	u8         reserved_at_10[0x4];
11709 	u8         sensor_count[0xc];
11710 
11711 	u8         sensor_warning_0[0x20];
11712 
11713 	u8         reserved_at_40[0x2a0];
11714 };
11715 
11716 struct mlx5_ifc_mtewe_ext_bits {
11717 	u8         reserved_at_0[0x4];
11718 	u8         last_sensor[0xc];
11719 	u8         reserved_at_10[0x4];
11720 	u8         sensor_count[0xc];
11721 
11722 	u8         sensor_warning_0[0x20];
11723 
11724 	u8         reserved_at_40[0x2a0];
11725 };
11726 
11727 struct mlx5_ifc_mtmp_bits {
11728 	u8         reserved_at_0[0x14];
11729 	u8         sensor_index[0xc];
11730 
11731 	u8         reserved_at_20[0x10];
11732 	u8         temperature[0x10];
11733 
11734 	u8         mte[0x1];
11735 	u8         mtr[0x1];
11736 	u8         reserved_at_42[0xe];
11737 	u8         max_temperature[0x10];
11738 
11739 	u8         tee[0x2];
11740 	u8         reserved_at_62[0xe];
11741 	u8         temperature_threshold_hi[0x10];
11742 
11743 	u8         reserved_at_80[0x10];
11744 	u8         temperature_threshold_lo[0x10];
11745 
11746 	u8         reserved_at_a0[0x20];
11747 
11748 	u8         sensor_name_hi[0x20];
11749 
11750 	u8         sensor_name_lo[0x20];
11751 };
11752 
11753 struct mlx5_ifc_mtmp_ext_bits {
11754 	u8         reserved_at_0[0x14];
11755 	u8         sensor_index[0xc];
11756 
11757 	u8         reserved_at_20[0x10];
11758 	u8         temperature[0x10];
11759 
11760 	u8         mte[0x1];
11761 	u8         mtr[0x1];
11762 	u8         reserved_at_42[0xe];
11763 	u8         max_temperature[0x10];
11764 
11765 	u8         tee[0x2];
11766 	u8         reserved_at_62[0xe];
11767 	u8         temperature_threshold_hi[0x10];
11768 
11769 	u8         reserved_at_80[0x10];
11770 	u8         temperature_threshold_lo[0x10];
11771 
11772 	u8         reserved_at_a0[0x20];
11773 
11774 	u8         sensor_name_hi[0x20];
11775 
11776 	u8         sensor_name_lo[0x20];
11777 };
11778 
11779 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
11780 	u8         opcode[0x10];
11781 	u8         uid[0x10];
11782 
11783 	u8         vhca_tunnel_id[0x10];
11784 	u8         obj_type[0x10];
11785 
11786 	u8         obj_id[0x20];
11787 
11788 	u8         reserved_at_60[0x20];
11789 };
11790 
11791 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
11792 	u8         status[0x8];
11793 	u8         reserved_at_8[0x18];
11794 
11795 	u8         syndrome[0x20];
11796 
11797 	u8         obj_id[0x20];
11798 
11799 	u8         reserved_at_60[0x20];
11800 };
11801 
11802 struct mlx5_ifc_umem_bits {
11803 	u8         reserved_at_0[0x80];
11804 
11805 	u8         reserved_at_80[0x1b];
11806 	u8         log_page_size[0x5];
11807 
11808 	u8         page_offset[0x20];
11809 
11810 	u8         num_of_mtt[0x40];
11811 
11812 	struct mlx5_ifc_mtt_bits  mtt[0];
11813 };
11814 
11815 struct mlx5_ifc_uctx_bits {
11816 	u8         cap[0x20];
11817 
11818 	u8         reserved_at_20[0x160];
11819 };
11820 
11821 struct mlx5_ifc_create_umem_in_bits {
11822 	u8         opcode[0x10];
11823 	u8         uid[0x10];
11824 
11825 	u8         reserved_at_20[0x10];
11826 	u8         op_mod[0x10];
11827 
11828 	u8         reserved_at_40[0x40];
11829 
11830 	struct mlx5_ifc_umem_bits  umem;
11831 };
11832 
11833 struct mlx5_ifc_create_uctx_in_bits {
11834 	u8         opcode[0x10];
11835 	u8         reserved_at_10[0x10];
11836 
11837 	u8         reserved_at_20[0x10];
11838 	u8         op_mod[0x10];
11839 
11840 	u8         reserved_at_40[0x40];
11841 
11842 	struct mlx5_ifc_uctx_bits  uctx;
11843 };
11844 
11845 struct mlx5_ifc_destroy_uctx_in_bits {
11846 	u8         opcode[0x10];
11847 	u8         reserved_at_10[0x10];
11848 
11849 	u8         reserved_at_20[0x10];
11850 	u8         op_mod[0x10];
11851 
11852 	u8         reserved_at_40[0x10];
11853 	u8         uid[0x10];
11854 
11855 	u8         reserved_at_60[0x20];
11856 };
11857 
11858 struct mlx5_ifc_mtrc_string_db_param_bits {
11859 	u8         string_db_base_address[0x20];
11860 
11861 	u8         reserved_at_20[0x8];
11862 	u8         string_db_size[0x18];
11863 };
11864 
11865 struct mlx5_ifc_mtrc_cap_bits {
11866 	u8         trace_owner[0x1];
11867 	u8         trace_to_memory[0x1];
11868 	u8         reserved_at_2[0x4];
11869 	u8         trc_ver[0x2];
11870 	u8         reserved_at_8[0x14];
11871 	u8         num_string_db[0x4];
11872 
11873 	u8         first_string_trace[0x8];
11874 	u8         num_string_trace[0x8];
11875 	u8         reserved_at_30[0x28];
11876 
11877 	u8         log_max_trace_buffer_size[0x8];
11878 
11879 	u8         reserved_at_60[0x20];
11880 
11881 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11882 
11883 	u8         reserved_at_280[0x180];
11884 };
11885 
11886 struct mlx5_ifc_mtrc_conf_bits {
11887 	u8         reserved_at_0[0x1c];
11888 	u8         trace_mode[0x4];
11889 	u8         reserved_at_20[0x18];
11890 	u8         log_trace_buffer_size[0x8];
11891 	u8         trace_mkey[0x20];
11892 	u8         reserved_at_60[0x3a0];
11893 };
11894 
11895 struct mlx5_ifc_mtrc_stdb_bits {
11896 	u8         string_db_index[0x4];
11897 	u8         reserved_at_4[0x4];
11898 	u8         read_size[0x18];
11899 	u8         start_offset[0x20];
11900 	u8         string_db_data[0];
11901 };
11902 
11903 struct mlx5_ifc_mtrc_ctrl_bits {
11904 	u8         trace_status[0x2];
11905 	u8         reserved_at_2[0x2];
11906 	u8         arm_event[0x1];
11907 	u8         reserved_at_5[0xb];
11908 	u8         modify_field_select[0x10];
11909 	u8         reserved_at_20[0x2b];
11910 	u8         current_timestamp52_32[0x15];
11911 	u8         current_timestamp31_0[0x20];
11912 	u8         reserved_at_80[0x180];
11913 };
11914 
11915 struct mlx5_ifc_affiliated_event_header_bits {
11916 	u8         reserved_at_0[0x10];
11917 	u8         obj_type[0x10];
11918 
11919 	u8         obj_id[0x20];
11920 };
11921 
11922 #define MLX5_FC_BULK_SIZE_FACTOR 128
11923 
11924 enum mlx5_fc_bulk_alloc_bitmask {
11925 	MLX5_FC_BULK_128   = (1 << 0),
11926 	MLX5_FC_BULK_256   = (1 << 1),
11927 	MLX5_FC_BULK_512   = (1 << 2),
11928 	MLX5_FC_BULK_1024  = (1 << 3),
11929 	MLX5_FC_BULK_2048  = (1 << 4),
11930 	MLX5_FC_BULK_4096  = (1 << 5),
11931 	MLX5_FC_BULK_8192  = (1 << 6),
11932 	MLX5_FC_BULK_16384 = (1 << 7),
11933 };
11934 
11935 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
11936 
11937 struct mlx5_ifc_ipsec_cap_bits {
11938 	u8         ipsec_full_offload[0x1];
11939 	u8         ipsec_crypto_offload[0x1];
11940 	u8         ipsec_esn[0x1];
11941 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
11942 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
11943 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
11944 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
11945 	u8         reserved_at_7[0x4];
11946 	u8         log_max_ipsec_offload[0x5];
11947 	u8         reserved_at_10[0x10];
11948 
11949 	u8         min_log_ipsec_full_replay_window[0x8];
11950 	u8         max_log_ipsec_full_replay_window[0x8];
11951 	u8         reserved_at_30[0x7d0];
11952 };
11953 
11954 enum {
11955 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11956 };
11957 
11958 enum {
11959 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11960 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11961 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11962 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11963 };
11964 
11965 enum {
11966 	MLX5_IPSEC_ASO_MODE              = 0x0,
11967 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11968 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
11969 };
11970 
11971 enum {
11972 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11973 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11974 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11975 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11976 };
11977 
11978 struct mlx5_ifc_ipsec_aso_bits {
11979 	u8         valid[0x1];
11980 	u8         reserved_at_201[0x1];
11981 	u8         mode[0x2];
11982 	u8         window_sz[0x2];
11983 	u8         soft_lft_arm[0x1];
11984 	u8         hard_lft_arm[0x1];
11985 	u8         remove_flow_enable[0x1];
11986 	u8         esn_event_arm[0x1];
11987 	u8         reserved_at_20a[0x16];
11988 
11989 	u8         remove_flow_pkt_cnt[0x20];
11990 
11991 	u8         remove_flow_soft_lft[0x20];
11992 
11993 	u8         reserved_at_260[0x80];
11994 
11995 	u8         mode_parameter[0x20];
11996 
11997 	u8         replay_protection_window[0x100];
11998 };
11999 
12000 struct mlx5_ifc_ipsec_obj_bits {
12001 	u8         modify_field_select[0x40];
12002 	u8         full_offload[0x1];
12003 	u8         reserved_at_41[0x1];
12004 	u8         esn_en[0x1];
12005 	u8         esn_overlap[0x1];
12006 	u8         reserved_at_44[0x2];
12007 	u8         icv_length[0x2];
12008 	u8         reserved_at_48[0x4];
12009 	u8         aso_return_reg[0x4];
12010 	u8         reserved_at_50[0x10];
12011 
12012 	u8         esn_msb[0x20];
12013 
12014 	u8         reserved_at_80[0x8];
12015 	u8         dekn[0x18];
12016 
12017 	u8         salt[0x20];
12018 
12019 	u8         implicit_iv[0x40];
12020 
12021 	u8         reserved_at_100[0x8];
12022 	u8         ipsec_aso_access_pd[0x18];
12023 	u8         reserved_at_120[0xe0];
12024 
12025 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12026 };
12027 
12028 struct mlx5_ifc_create_ipsec_obj_in_bits {
12029 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12030 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12031 };
12032 
12033 enum {
12034 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = 1 << 0,
12035 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = 1 << 1,
12036 };
12037 
12038 struct mlx5_ifc_query_ipsec_obj_out_bits {
12039 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12040 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12041 };
12042 
12043 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12044 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12045 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12046 };
12047 
12048 enum {
12049 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12050 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12051 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12052 };
12053 #endif /* MLX5_IFC_H */
12054