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Searched refs:m2_frac (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dbxt_dpio_phy_regs.h75 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) argument
H A Dvlv_dpio_phy_regs.h200 #define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) argument
H A Dintel_dpll_mgr.c3200 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_ddi_mg_pll_get_freq() local
3211 m2_frac = hw_state->mg_pll_bias & in icl_ddi_mg_pll_get_freq()
3213 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; in icl_ddi_mg_pll_get_freq()
3215 m2_frac = 0; in icl_ddi_mg_pll_get_freq()
3222 m2_frac = hw_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3224 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; in icl_ddi_mg_pll_get_freq()
3226 m2_frac = 0; in icl_ddi_mg_pll_get_freq()
3262 (((u64)m1 * m2_frac * ref_clock) >> 22); in icl_ddi_mg_pll_get_freq()
H A Dintel_dpll.c2040 u32 m2_frac; in chv_prepare_pll() local
2042 m2_frac = clock->m2 & 0x3fffff; in chv_prepare_pll()
2064 DPIO_CHV_M2_FRAC_DIV(m2_frac)); in chv_prepare_pll()
2070 if (m2_frac) in chv_prepare_pll()
2079 if (!m2_frac) in chv_prepare_pll()