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Searched refs:lut_bank_a (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
H A Ddcn401_mpc.c121 …pc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id) in mpc401_populate_lut() argument
123 const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; in mpc401_populate_lut()
239 bool lut_bank_a, in mpc401_program_lut_mode() argument
251 REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2); in mpc401_program_lut_mode()
261 REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); in mpc401_program_lut_mode()
277 MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1); in mpc401_program_lut_mode()
282 …ram_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id) in mpc401_program_lut_read_write_control() argument
289 …REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); in mpc401_program_lut_read_write_control()
292 mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); in mpc401_program_lut_read_write_control()
295 mpc32_configure_post1dlut(mpc, lut_bank_a, mpcc_id); in mpc401_program_lut_read_write_control()
H A Ddcn401_mpc.h209 bool lut_bank_a, int mpcc_id);
215 bool lut_bank_a,
221 bool lut_bank_a,
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h1005 bool lut_bank_a, int mpcc_id);
1022 …void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a,…
1041 bool lut_bank_a, int mpcc_id);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.h55 bool lut_bank_a);
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h184 bool lut_bank_a);
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1362 bool lut_bank_a; member
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c2968 surface->lut_bank_a = !surface->lut_bank_a; in copy_surface_update_to_plane()