Home
last modified time | relevance | path

Searched refs:link_res (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_8b_10b.c115 const struct link_resource *link_res, in decide_8b_10b_training_settings() argument
137 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); in decide_8b_10b_training_settings()
185 const struct link_resource *link_res, in set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence() argument
207 dp_set_hw_training_pattern(link, link_res, DP_TRAINING_PATTERN_SEQUENCE_2, DPRX); in set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence()
209 dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX); in set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence()
222 const struct link_resource *link_res, in perform_8b_10b_clock_recovery_sequence() argument
243 dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset); in perform_8b_10b_clock_recovery_sequence()
257 link_res, in perform_8b_10b_clock_recovery_sequence()
342 const struct link_resource *link_res, in perform_8b_10b_channel_equalization_sequence() argument
361 dp_set_hw_training_pattern(link, link_res, tr_pattern, offset); in perform_8b_10b_channel_equalization_sequence()
[all …]
H A Dlink_dp_training_auxless.h33 const struct link_resource *link_res,
H A Dlink_dp_training_fixed_vs_pe_retimer.h33 const struct link_resource *link_res,
H A Dlink_dp_training_dpia.h40 const struct link_resource *link_res,
H A Dlink_dp_capability.c381 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in dp_is_128b_132b_signal()
383 pipe_ctx->link_res.hpo_dp_link_enc && in dp_is_128b_132b_signal()
1339 struct link_resource link_res = {0}; in apply_usbc_combo_phy_reset_wa() local
1342 dp_enable_link_phy(link, &link_res, link->connector_signal, in apply_usbc_combo_phy_reset_wa()
1344 dp_disable_link_phy(link, &link_res, link->connector_signal); in apply_usbc_combo_phy_reset_wa()
2439 struct link_resource link_res; in dp_verify_link_cap() local
2452 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings)) in dp_verify_link_cap()
2458 &link_res, in dp_verify_link_cap()
2465 &link_res, in dp_verify_link_cap()
2485 dp_disable_link_phy(link, &link_res, link->connector_signal); in dp_verify_link_cap()
/linux/drivers/soundwire/
H A Dintel.c75 void __iomem *s = sdw->link_res->shim; in intel_reg_show()
76 void __iomem *a = sdw->link_res->alh; in intel_reg_show()
209 void __iomem *shim = sdw->link_res->shim; in intel_shim_glue_to_master_ip()
240 void __iomem *shim = sdw->link_res->shim; in intel_shim_master_ip_to_glue()
260 void __iomem *shim = sdw->link_res->shim; in intel_shim_init()
296 shim = sdw->link_res->shim; in intel_shim_check_wake()
304 void __iomem *shim = sdw->link_res->shim; in intel_shim_wake()
308 mutex_lock(sdw->link_res->shim_lock); in intel_shim_wake()
325 mutex_unlock(sdw->link_res->shim_lock); in intel_shim_wake()
330 void __iomem *shim = sdw->link_res->shim; in intel_check_cmdsync_unlocked()
[all …]
H A Dintel.h78 struct sdw_intel_link_res *link_res; member
133 #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \
134 (sdw)->link_res->hw_ops->cb)
135 #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb)
H A Dintel_init.c64 link = &ldev->link_res; in intel_link_dev_register()
134 if (!ldev->link_res.clock_stop_quirks) in sdw_intel_cleanup()
135 pm_runtime_put_noidle(ldev->link_res.dev); in sdw_intel_cleanup()
237 link = &ldev->link_res; in sdw_intel_probe_controller()
308 if (!ldev->link_res.clock_stop_quirks) { in sdw_intel_startup_controller()
315 pm_runtime_get_noresume(ldev->link_res.dev); in sdw_intel_startup_controller()
H A Dintel_ace2x_debugfs.c40 void __iomem *s = sdw->link_res->shim; in intel_reg_show()
41 void __iomem *vs_s = sdw->link_res->shim_vs; in intel_reg_show()
79 if (sdw->link_res->mic_privacy) { in intel_reg_show()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink_hwss.h55 const struct link_resource *link_res,
60 const struct link_resource *link_res,
63 const struct link_resource *link_res,
67 const struct link_resource *link_res,
81 const struct link_resource *link_res,
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_resource.c33 struct link_resource *link_res) in link_get_cur_link_res() argument
38 memset(link_res, 0, sizeof(*link_res)); in link_get_cur_link_res()
44 *link_res = pipe->link_res; in link_get_cur_link_res()
H A Dlink_dpms.c159 struct link_resource link_res = {0}; in link_set_all_streams_dpms_off_for_link() local
185 dp_disable_link_phy(link, &link_res, link->connector_signal); in link_set_all_streams_dpms_off_for_link()
529 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in update_psp_stream_config()
560 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; in update_psp_stream_config()
1226 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in deallocate_mst_payload()
1279 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, in deallocate_mst_payload()
1306 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in allocate_mst_payload()
1341 &pipe_ctx->link_res, in allocate_mst_payload()
1511 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in update_sst_payload()
1555 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, in update_sst_payload()
[all …]
H A Dlink_hwss_hpo_frl.c54 const struct link_resource *link_res) in can_use_hpo_frl_link_hwss() argument
56 return link_res->hpo_frl_link_enc != NULL; in can_use_hpo_frl_link_hwss()
/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_dpia.h35 const struct link_resource *link_res);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.h48 void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum si…
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2734 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; in add_hpo_dp_link_enc_to_ctx()
2736 return pipe_ctx->link_res.hpo_dp_link_enc != NULL; in add_hpo_dp_link_enc_to_ctx()
2749 pipe_ctx->link_res.hpo_dp_link_enc = NULL; in remove_hpo_dp_link_enc_from_ctx()
2868 if (pipe_ctx && pipe_ctx->link_res.dio_link_enc == pool->link_encoders[old_encoder]) in swap_dio_link_enc_to_muxable_ctx()
2869 pipe_ctx->link_res.dio_link_enc = pool->link_encoders[new_encoder]; in swap_dio_link_enc_to_muxable_ctx()
2912 pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index]; in add_dio_link_enc_to_ctx()
2914 return pipe_ctx->link_res.dio_link_enc != NULL; in add_dio_link_enc_to_ctx()
2928 pipe_ctx->link_res.dio_link_enc = NULL; in remove_dio_link_enc_from_ctx()
5025 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc) in pipe_need_reprogram()
5030 if (pipe_ctx_old->link_res.dio_link_enc != pipe_ctx->link_res.dio_link_enc) in pipe_need_reprogram()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c728 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in dce110_enable_stream()
1139 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); in dce110_enable_audio_stream()
1178 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); in dce110_disable_audio_stream()
1205 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in dce110_disable_stream()
1210 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in dce110_disable_stream()
1648 link, &pipe_ctx->link_res); in dce110_apply_single_controller_ctx_to_hw()
3358 const struct link_resource *link_res, in dce110_enable_lvds_link_output() argument
3362 (void)link_res; in dce110_enable_lvds_link_output()
3371 const struct link_resource *link_res, in dce110_enable_tmds_link_output() argument
3377 (void)link_res; in dce110_enable_tmds_link_output()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h97 const struct link_resource *link_res,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_utils.c190 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in check_dp2p0_output_encoder()
192 pipe_ctx->link_res.hpo_dp_link_enc && in check_dp2p0_output_encoder()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c162 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in is_dp2p0_output_encoder()
165 pipe_ctx->link_res.hpo_dp_link_enc && in is_dp2p0_output_encoder()
H A Ddml2_translation_helper.c1291 current_pipe_context->link_res.hpo_dp_link_enc && in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
1294 current_pipe_context->link_res.hpo_dp_link_enc->inst; in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c846 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in dcn401_enable_stream()
853 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in dcn401_enable_stream()
937 const struct link_resource *link_res, in dcn401_disable_link_output() argument
941 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); in dcn401_disable_link_output()
955 link_hwss->disable_link_output(link, link_res, signal); in dcn401_disable_link_output()
1877 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); in dcn401_reset_back_end_for_pipe()
1935 &pipe_ctx->link_res, pipe_ctx->stream->signal); in dcn401_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1972 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); in dcn32_apply_merge_split_flags_helper()
1988 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); in dcn32_apply_merge_split_flags_helper()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1259 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in get_pixel_clock_parameters()