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Searched refs:lgm_get_clk_val (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/x86/
H A Dclk-cgu-pll.c45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
60 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); in lgm_pll_is_enabled()
H A Dclk-cgu.c46 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_get_parent()
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
283 ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1); in lgm_clk_gate_is_enabled()
398 div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
400 div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
402 exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
470 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_set_rate()
501 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_round_rate()
518 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_round_rate()
H A Dclk-cgu.h308 static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg, in lgm_get_clk_val() function