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Searched refs:length_dw (Results 1 – 25 of 43) sorted by relevance

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/linux/drivers/gpu/drm/radeon/
H A Dsi_dma.c78 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_vm_copy_pages()
80 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pages()
81 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pages()
82 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
83 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
119 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); in si_dma_vm_write_pages()
120 ib->ptr[ib->length_dw++] = pe; in si_dma_vm_write_pages()
121 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
132 ib->ptr[ib->length_dw++] = value; in si_dma_vm_write_pages()
133 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
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H A Dni_dma.c145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
326 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in cayman_dma_vm_copy_pages()
328 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cayman_dma_vm_copy_pages()
329 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cayman_dma_vm_copy_pages()
330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
331 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
367 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, in cayman_dma_vm_write_pages()
369 ib->ptr[ib->length_dw++] = pe; in cayman_dma_vm_write_pages()
370 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
381 ib->ptr[ib->length_dw++] = value; in cayman_dma_vm_write_pages()
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H A Dradeon_cs.c95 p->nrelocs = chunk->length_dw / 4; in radeon_cs_parser_relocs()
313 p->chunks[i].length_dw = user_chunk.length_dw; in radeon_cs_parser_init()
320 if (p->chunks[i].length_dw == 0) in radeon_cs_parser_init()
326 if (p->chunks[i].length_dw == 0) in radeon_cs_parser_init()
332 if (p->chunks[i].length_dw == 0) in radeon_cs_parser_init()
336 size = p->chunks[i].length_dw; in radeon_cs_parser_init()
357 if (p->chunks[i].length_dw > 1) in radeon_cs_parser_init()
359 if (p->chunks[i].length_dw > 2) in radeon_cs_parser_init()
562 if (parser->const_ib.length_dw) { in radeon_cs_ib_vm_chunk()
628 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { in radeon_cs_ib_fill()
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H A Dcik_sdma.c156 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
731 ib.length_dw = 5; in cik_sdma_ib_test()
812 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, in cik_sdma_vm_copy_pages()
814 ib->ptr[ib->length_dw++] = bytes; in cik_sdma_vm_copy_pages()
815 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in cik_sdma_vm_copy_pages()
816 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pages()
817 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages()
818 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pages()
819 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pages()
855 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, in cik_sdma_vm_write_pages()
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H A Dradeon_vm.c409 ib.length_dw = 0; in radeon_vm_clear_bo()
413 WARN_ON(ib.length_dw > 64); in radeon_vm_clear_bo()
661 ib.length_dw = 0; in radeon_vm_update_page_directory()
698 if (ib.length_dw != 0) { in radeon_vm_update_page_directory()
702 WARN_ON(ib.length_dw > ndw); in radeon_vm_update_page_directory()
999 ib.length_dw = 0; in radeon_vm_bo_update()
1017 WARN_ON(ib.length_dw > ndw); in radeon_vm_bo_update()
H A Dr600_dma.c362 ib.length_dw = 4; in r600_dma_ib_test()
426 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
H A Devergreen_dma.c89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
H A Dradeon_ib.c133 if (!ib->length_dw || !ring->ready) { in radeon_ib_schedule()
H A Dradeon_trace.h41 __entry->dw = p->chunk_ib->length_dw;
H A Dr600_cs.c2328 } while (p->idx < p->chunk_ib->length_dw); in r600_cs_parse()
2330 for (r = 0; r < p->ib.length_dw; r++) { in r600_cs_parse()
2396 if (p->idx >= ib_chunk->length_dw) { in r600_dma_cs_parse()
2398 p->idx, ib_chunk->length_dw); in r600_dma_cs_parse()
2534 } while (p->idx < p->chunk_ib->length_dw); in r600_dma_cs_parse()
2536 for (r = 0; r < p->ib->length_dw; r++) { in r600_dma_cs_parse()
H A Devergreen_cs.c2869 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2871 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2901 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2903 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
3308 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3310 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3650 } while (idx < ib->length_dw); in evergreen_ib_parse()
3756 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.c649 ib->length_dw = 16; in amdgpu_vcn_dec_send_msg()
769 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ in amdgpu_vcn_unified_ring_ib_header()
770 ib->ptr[ib->length_dw++] = 0x30000002; in amdgpu_vcn_unified_ring_ib_header()
771 ib_checksum = &ib->ptr[ib->length_dw++]; in amdgpu_vcn_unified_ring_ib_header()
772 ib->ptr[ib->length_dw++] = ib_pack_in_dw; in amdgpu_vcn_unified_ring_ib_header()
774 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ in amdgpu_vcn_unified_ring_ib_header()
775 ib->ptr[ib->length_dw++] = 0x30000001; in amdgpu_vcn_unified_ring_ib_header()
776 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; in amdgpu_vcn_unified_ring_ib_header()
777 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); in amdgpu_vcn_unified_ring_ib_header()
819 ib->length_dw in amdgpu_vcn_dec_sw_send_msg()
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H A Dsdma_v7_0.c290 amdgpu_ring_write(ring, ib->length_dw); in sdma_v7_0_ring_emit_ib()
1033 ib.length_dw = 8; in sdma_v7_0_ring_test_ib()
1081 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | in sdma_v7_0_vm_copy_pte()
1085 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v7_0_vm_copy_pte()
1086 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v7_0_vm_copy_pte()
1087 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v7_0_vm_copy_pte()
1088 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v7_0_vm_copy_pte()
1089 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v7_0_vm_copy_pte()
1090 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v7_0_vm_copy_pte()
1091 ib->ptr[ib->length_dw in sdma_v7_0_vm_copy_pte()
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H A Dsdma_v6_0.c288 amdgpu_ring_write(ring, ib->length_dw); in sdma_v6_0_ring_emit_ib()
1018 ib.length_dw = 8; in sdma_v6_0_ring_test_ib()
1066 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | in sdma_v6_0_vm_copy_pte()
1068 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v6_0_vm_copy_pte()
1069 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v6_0_vm_copy_pte()
1070 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v6_0_vm_copy_pte()
1071 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v6_0_vm_copy_pte()
1072 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v6_0_vm_copy_pte()
1073 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v6_0_vm_copy_pte()
1094 ib->ptr[ib->length_dw in sdma_v6_0_vm_write_pte()
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H A Dsdma_v7_1.c284 amdgpu_ring_write(ring, ib->length_dw); in sdma_v7_1_ring_emit_ib()
1023 ib.length_dw = 8; in sdma_v7_1_ring_test_ib()
1071 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | in sdma_v7_1_vm_copy_pte()
1074 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v7_1_vm_copy_pte()
1075 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v7_1_vm_copy_pte()
1076 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v7_1_vm_copy_pte()
1077 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v7_1_vm_copy_pte()
1078 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v7_1_vm_copy_pte()
1079 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v7_1_vm_copy_pte()
1100 ib->ptr[ib->length_dw in sdma_v7_1_vm_write_pte()
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H A Dsdma_v4_0.c821 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
1547 ib.length_dw = 8; in sdma_v4_0_ring_test_ib()
1591 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v4_0_vm_copy_pte()
1593 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v4_0_vm_copy_pte()
1594 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v4_0_vm_copy_pte()
1595 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v4_0_vm_copy_pte()
1596 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v4_0_vm_copy_pte()
1597 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v4_0_vm_copy_pte()
1598 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v4_0_vm_copy_pte()
1619 ib->ptr[ib->length_dw in sdma_v4_0_vm_write_pte()
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H A Dgfx_v9_0.c1252 ib.length_dw = 5; in gfx_v9_0_ring_test_ib()
4709 ib.length_dw = 0; in gfx_v9_0_do_edc_gpr_workarounds()
4714 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4715 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) in gfx_v9_0_do_edc_gpr_workarounds()
4717 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; in gfx_v9_0_do_edc_gpr_workarounds()
4721 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4722 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) in gfx_v9_0_do_edc_gpr_workarounds()
4724 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); in gfx_v9_0_do_edc_gpr_workarounds()
4725 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); in gfx_v9_0_do_edc_gpr_workarounds()
4728 ib.ptr[ib.length_dw in gfx_v9_0_do_edc_gpr_workarounds()
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H A Damdgpu_cs.h39 uint32_t length_dw; member
H A Dvcn_sw_ring.c53 amdgpu_ring_write(ring, ib->length_dw); in vcn_dec_sw_ring_emit_ib()
H A Damdgpu_ring.c149 u32 count = ib->length_dw & align_mask; in amdgpu_ring_generic_pad_ib()
154 memset32(&ib->ptr[ib->length_dw], ring->funcs->nop, count); in amdgpu_ring_generic_pad_ib()
156 ib->length_dw += count; in amdgpu_ring_generic_pad_ib()
H A Damdgpu_jpeg.c212 ib->length_dw = 16; in amdgpu_jpeg_dec_set_reg()
571 for (i = 0; i < ib->length_dw ; i += 2) { in amdgpu_jpeg_dec_parse_cs()
H A Damdgpu_vpe.c543 amdgpu_ring_write(ring, ib->length_dw); in vpe_ring_emit_fence()
857 ib.length_dw = 8; in vpe_ring_test_ib()
H A Duvd_v3_1.c97 amdgpu_ring_write(ring, ib->length_dw); in uvd_v3_1_ring_emit_ib()
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hw.c469 le16_to_cpu(p_command->length_dw), in qed_dmae_post_command()
484 le16_to_cpu(p_command->length_dw), in qed_dmae_post_command()
616 u32 length_dw) in qed_dmae_execute_sub_operation() argument
634 length_dw * sizeof(u32)); in qed_dmae_execute_sub_operation()
655 cmd->length_dw = cpu_to_le16((u16)length_dw); in qed_dmae_execute_sub_operation()
664 src_addr, dst_addr, length_dw); in qed_dmae_execute_sub_operation()
671 length_dw * sizeof(u32)); in qed_dmae_execute_sub_operation()
/linux/include/uapi/drm/
H A Dradeon_drm.h969 __u32 length_dw; member

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