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Searched refs:layers (Results 1 – 25 of 133) sorted by relevance

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/linux/security/landlock/
H A Druleset.c112 const struct landlock_layer (*const layers)[], const u32 num_layers, in create_rule() argument
127 new_rule = kzalloc(struct_size(new_rule, layers, new_num_layers), in create_rule()
141 memcpy(new_rule->layers, layers, in create_rule()
142 flex_array_size(new_rule, layers, num_layers)); in create_rule()
145 new_rule->layers[new_rule->num_layers - 1] = *new_layer; in create_rule()
209 const struct landlock_layer (*const layers)[], in insert_rule() argument
219 if (WARN_ON_ONCE(!layers)) in insert_rule()
248 if ((*layers)[0].level == 0) { in insert_rule()
255 if (WARN_ON_ONCE(this->layers[0].level != 0)) in insert_rule()
257 this->layers[0].access |= (*layers)[0].access; in insert_rule()
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/linux/drivers/edac/
H A Damd76x_edac.c237 struct edac_mc_layer layers[2]; in amd76x_probe1() local
246 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in amd76x_probe1()
247 layers[0].size = AMD76X_NR_CSROWS; in amd76x_probe1()
248 layers[0].is_virt_csrow = true; in amd76x_probe1()
249 layers[1].type = EDAC_MC_LAYER_CHANNEL; in amd76x_probe1()
250 layers[1].size = 1; in amd76x_probe1()
251 layers[1].is_virt_csrow = false; in amd76x_probe1()
252 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in amd76x_probe1()
H A Dpasemi_edac.c183 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
200 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
201 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
202 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
203 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
204 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
205 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
206 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
H A Di82860_edac.c187 struct edac_mc_layer layers[2]; in i82860_probe1() local
200 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i82860_probe1()
201 layers[0].size = 2; in i82860_probe1()
202 layers[0].is_virt_csrow = true; in i82860_probe1()
203 layers[1].type = EDAC_MC_LAYER_SLOT; in i82860_probe1()
204 layers[1].size = 8; in i82860_probe1()
205 layers[1].is_virt_csrow = true; in i82860_probe1()
206 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82860_probe1()
H A Dr82600_edac.c271 struct edac_mc_layer layers[2]; in r82600_probe1() local
285 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in r82600_probe1()
286 layers[0].size = R82600_NR_CSROWS; in r82600_probe1()
287 layers[0].is_virt_csrow = true; in r82600_probe1()
288 layers[1].type = EDAC_MC_LAYER_CHANNEL; in r82600_probe1()
289 layers[1].size = R82600_NR_CHANS; in r82600_probe1()
290 layers[1].is_virt_csrow = false; in r82600_probe1()
291 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in r82600_probe1()
H A Dhighbank_mc_edac.c149 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
163 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
164 layers[0].size = 1; in highbank_mc_probe()
165 layers[0].is_virt_csrow = true; in highbank_mc_probe()
166 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
167 layers[1].size = 1; in highbank_mc_probe()
168 layers[1].is_virt_csrow = false; in highbank_mc_probe()
169 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
H A Di82443bxgx_edac.c234 struct edac_mc_layer layers[2]; in i82443bxgx_edacmc_probe1() local
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82443bxgx_edacmc_probe1()
249 layers[0].size = I82443BXGX_NR_CSROWS; in i82443bxgx_edacmc_probe1()
250 layers[0].is_virt_csrow = true; in i82443bxgx_edacmc_probe1()
251 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82443bxgx_edacmc_probe1()
252 layers[1].size = I82443BXGX_NR_CHANS; in i82443bxgx_edacmc_probe1()
253 layers[1].is_virt_csrow = false; in i82443bxgx_edacmc_probe1()
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82443bxgx_edacmc_probe1()
H A Daspeed_edac.c282 struct edac_mc_layer layers[2]; in aspeed_probe() local
307 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in aspeed_probe()
308 layers[0].size = 1; in aspeed_probe()
309 layers[0].is_virt_csrow = true; in aspeed_probe()
310 layers[1].type = EDAC_MC_LAYER_CHANNEL; in aspeed_probe()
311 layers[1].size = 1; in aspeed_probe()
312 layers[1].is_virt_csrow = false; in aspeed_probe()
314 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in aspeed_probe()
H A Di3000_edac.c313 struct edac_mc_layer layers[2]; in i3000_probe1() local
356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3000_probe1()
357 layers[0].size = I3000_RANKS / nr_channels; in i3000_probe1()
358 layers[0].is_virt_csrow = true; in i3000_probe1()
359 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3000_probe1()
360 layers[1].size = nr_channels; in i3000_probe1()
361 layers[1].is_virt_csrow = false; in i3000_probe1()
362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i3000_probe1()
H A Di82875p_edac.c391 struct edac_mc_layer layers[2]; in i82875p_probe1() local
406 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82875p_probe1()
407 layers[0].size = I82875P_NR_CSROWS(nr_chans); in i82875p_probe1()
408 layers[0].is_virt_csrow = true; in i82875p_probe1()
409 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82875p_probe1()
410 layers[1].size = nr_chans; in i82875p_probe1()
411 layers[1].is_virt_csrow = false; in i82875p_probe1()
412 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82875p_probe1()
H A Dx38_edac.c322 struct edac_mc_layer layers[2]; in x38_probe1() local
338 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in x38_probe1()
339 layers[0].size = X38_RANKS; in x38_probe1()
340 layers[0].is_virt_csrow = true; in x38_probe1()
341 layers[1].type = EDAC_MC_LAYER_CHANNEL; in x38_probe1()
342 layers[1].size = x38_channel_num; in x38_probe1()
343 layers[1].is_virt_csrow = false; in x38_probe1()
344 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in x38_probe1()
H A Di3200_edac.c340 struct edac_mc_layer layers[2]; in i3200_probe1() local
355 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3200_probe1()
356 layers[0].size = I3200_DIMMS; in i3200_probe1()
357 layers[0].is_virt_csrow = true; in i3200_probe1()
358 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3200_probe1()
359 layers[1].size = nr_channels; in i3200_probe1()
360 layers[1].is_virt_csrow = false; in i3200_probe1()
361 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in i3200_probe1()
H A Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
234 layers[0].size = 1; in octeon_lmc_edac_probe()
235 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
H A De7xxx_edac.c424 struct edac_mc_layer layers[2]; in e7xxx_probe1() local
443 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e7xxx_probe1()
444 layers[0].size = E7XXX_NR_CSROWS; in e7xxx_probe1()
445 layers[0].is_virt_csrow = true; in e7xxx_probe1()
446 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e7xxx_probe1()
447 layers[1].size = drc_chan + 1; in e7xxx_probe1()
448 layers[1].is_virt_csrow = false; in e7xxx_probe1()
449 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e7xxx_probe1()
H A Di82975x_edac.c467 struct edac_mc_layer layers[2]; in i82975x_probe1() local
540 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82975x_probe1()
541 layers[0].size = I82975X_NR_DIMMS; in i82975x_probe1()
542 layers[0].is_virt_csrow = true; in i82975x_probe1()
543 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82975x_probe1()
544 layers[1].size = I82975X_NR_CSROWS(chans); in i82975x_probe1()
545 layers[1].is_virt_csrow = false; in i82975x_probe1()
546 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82975x_probe1()
H A Dal_mc_edac.c219 struct edac_mc_layer layers[1]; in al_mc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in al_mc_edac_probe()
234 layers[0].size = 1; in al_mc_edac_probe()
235 layers[0].is_virt_csrow = false; in al_mc_edac_probe()
236 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in al_mc_edac_probe()
H A Dbluefield_edac.c356 struct edac_mc_layer layers[1]; in bluefield_edac_mc_probe() local
384 layers[0].type = EDAC_MC_LAYER_SLOT; in bluefield_edac_mc_probe()
385 layers[0].size = dimm_count; in bluefield_edac_mc_probe()
386 layers[0].is_virt_csrow = true; in bluefield_edac_mc_probe()
388 mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv)); in bluefield_edac_mc_probe()
H A Dcpc925_edac.c910 struct edac_mc_layer layers[2]; in cpc925_probe() local
948 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cpc925_probe()
949 layers[0].size = CPC925_NR_CSROWS; in cpc925_probe()
950 layers[0].is_virt_csrow = true; in cpc925_probe()
951 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cpc925_probe()
952 layers[1].size = nr_channels; in cpc925_probe()
953 layers[1].is_virt_csrow = false; in cpc925_probe()
954 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in cpc925_probe()
H A Die31200_edac.c462 struct edac_mc_layer layers[2]; in ie31200_register_mci() local
469 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ie31200_register_mci()
470 layers[0].size = IE31200_RANKS_PER_CHANNEL; in ie31200_register_mci()
471 layers[0].is_virt_csrow = true; in ie31200_register_mci()
472 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ie31200_register_mci()
473 layers[1].size = nr_channels; in ie31200_register_mci()
474 layers[1].is_virt_csrow = false; in ie31200_register_mci()
475 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, in ie31200_register_mci()
H A Dti_edac.c237 struct edac_mc_layer layers[1]; in ti_edac_probe() local
251 layers[0].type = EDAC_MC_LAYER_ALL_MEM; in ti_edac_probe()
252 layers[0].size = 1; in ti_edac_probe()
259 mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac)); in ti_edac_probe()
/linux/drivers/media/dvb-frontends/
H A Dtc90522.c201 int layers; in tc90522s_get_frontend() local
209 layers = 0; in tc90522s_get_frontend()
236 layers = (v > 0) ? 2 : 1; in tc90522s_get_frontend()
284 stats->len = layers; in tc90522s_get_frontend()
287 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
290 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
298 stats->len = layers; in tc90522s_get_frontend()
300 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
303 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
336 int layers; in tc90522t_get_frontend() local
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/linux/drivers/parisc/
H A Dpdc_stable.c358 for (i = 0; i < 6 && devpath->layers[i]; i++) in pdcspath_layer_read()
359 out += sprintf(out, "%u ", devpath->layers[i]); in pdcspath_layer_read()
381 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ in pdcspath_layer_write() local
393 memset(&layers, 0, sizeof(layers)); in pdcspath_layer_write()
398 layers[0] = simple_strtoul(in, NULL, 10); in pdcspath_layer_write()
399 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); in pdcspath_layer_write()
405 layers[i] = simple_strtoul(temp, NULL, 10); in pdcspath_layer_write()
406 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); in pdcspath_layer_write()
414 memcpy(&entry->devpath.layers, &layers, sizeof(layers)); in pdcspath_layer_write()
/linux/fs/overlayfs/
H A Dsuper.c1028 struct ovl_fs_context *ctx, struct ovl_layer *layers) in ovl_get_layers() argument
1114 layers[ofs->numlayer].trap = trap; in ovl_get_layers()
1115 layers[ofs->numlayer].mnt = mnt; in ovl_get_layers()
1116 layers[ofs->numlayer].idx = ofs->numlayer; in ovl_get_layers()
1117 layers[ofs->numlayer].fsid = fsid; in ovl_get_layers()
1118 layers[ofs->numlayer].fs = &ofs->fs[fsid]; in ovl_get_layers()
1177 struct ovl_layer *layers) in ovl_get_lowerstack() argument
1213 err = ovl_get_layers(sb, ofs, ctx, layers); in ovl_get_lowerstack()
1228 lowerstack[i].layer = &ofs->layers[i + 1]; in ovl_get_lowerstack()
1299 ofs->layers[i].mnt->mnt_root, in ovl_check_overlapping_layers()
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/linux/Documentation/driver-api/fpga/
H A Dintro.rst9 * The FPGA subsystem separates upper layers (userspace interfaces and
10 enumeration) from lower layers that know how to program a specific
13 * Code should not be shared between upper and lower layers. This
/linux/Documentation/scsi/
H A Dscsi_eh.rst152 Note that this does not mean lower layers are quiescent. If a LLDD
153 completed a scmd with error status, the LLDD and lower layers are
155 has timed out, unless hostt->eh_timed_out() made lower layers forget
157 active as long as lower layers are concerned and completion could
206 lower layers and lower layers are ready to process or fail the scmd
364 that lower layers have forgotten about the scmd and we can
373 and STU doesn't make lower layers forget about those
375 if STU succeeds leaving lower layers in an inconsistent
428 On completion, the handler should have made lower layers forget about
468 - Know that timed out scmds are still active on lower layers. Make
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