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Searched refs:layers (Results 1 – 25 of 115) sorted by relevance

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/linux/security/landlock/
H A Druleset.c117 const struct landlock_layer (*layers)[], const u32 num_layers, in create_rule() argument
132 new_rule = kzalloc_flex(*new_rule, layers, new_num_layers, in create_rule()
146 memcpy(new_rule->layers, layers, in create_rule()
147 flex_array_size(new_rule, layers, num_layers)); in create_rule()
150 new_rule->layers[new_rule->num_layers - 1] = *new_layer; in create_rule()
199 const struct landlock_layer (*layers)[], in landlock_store_rule() argument
208 if (WARN_ON_ONCE(!layers)) in landlock_store_rule()
237 if ((*layers)[0].level == 0) { in landlock_store_rule()
244 if (WARN_ON_ONCE(this->layers[0].level != 0)) in landlock_store_rule()
246 this->layers[0].access |= (*layers)[0].access; in landlock_store_rule()
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H A Ddomain.c182 const struct landlock_layer *const layer = &rule->layers[i]; in landlock_unmask_layers()
185 masks->layers[layer->level - 1].access &= ~layer->access; in landlock_unmask_layers()
190 masks->layers[layer->level - 1].quiet = true; in landlock_unmask_layers()
194 for (size_t i = 0; i < ARRAY_SIZE(masks->layers); i++) { in landlock_unmask_layers()
195 if (masks->layers[i].access) in landlock_unmask_layers()
252 masks->layers[i].access = access_request & handled; in landlock_init_layer_masks()
253 handled_accesses |= masks->layers[i].access; in landlock_init_layer_masks()
255 masks->layers[i].quiet = false; in landlock_init_layer_masks()
258 for (size_t i = domain->num_layers; i < ARRAY_SIZE(masks->layers); in landlock_init_layer_masks()
260 masks->layers[i].access = 0; in landlock_init_layer_masks()
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H A Dfs.c457 for (size_t i = 0; i < ARRAY_SIZE(new_parent->layers); i++) { in may_refer()
458 access_mask_t child_access = src_parent->layers[i].access & in may_refer()
459 src_child->layers[i].access; in may_refer()
460 access_mask_t parent_access = new_parent->layers[i].access; in may_refer()
506 .layers[0].access = LANDLOCK_ACCESS_FS_EXECUTE | in test_no_more_access()
510 .layers[0].access = LANDLOCK_ACCESS_FS_EXECUTE | in test_no_more_access()
514 .layers[0].access = LANDLOCK_ACCESS_FS_EXECUTE, in test_no_more_access()
517 .layers[1].access = LANDLOCK_ACCESS_FS_EXECUTE, in test_no_more_access()
520 .layers[0].access = LANDLOCK_ACCESS_FS_EXECUTE, in test_no_more_access()
521 .layers[1].access = LANDLOCK_ACCESS_FS_EXECUTE, in test_no_more_access()
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H A Druleset.h118 struct landlock_layer layers[] __counted_by(num_layers);
213 const struct landlock_layer (*layers)[],
/linux/drivers/edac/
H A Dpasemi_edac.c183 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
200 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
201 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
202 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
203 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
204 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
205 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
206 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
H A Dhighbank_mc_edac.c149 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
163 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
164 layers[0].size = 1; in highbank_mc_probe()
165 layers[0].is_virt_csrow = true; in highbank_mc_probe()
166 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
167 layers[1].size = 1; in highbank_mc_probe()
168 layers[1].is_virt_csrow = false; in highbank_mc_probe()
169 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
H A Daspeed_edac.c280 struct edac_mc_layer layers[2]; in aspeed_probe() local
305 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in aspeed_probe()
306 layers[0].size = 1; in aspeed_probe()
307 layers[0].is_virt_csrow = true; in aspeed_probe()
308 layers[1].type = EDAC_MC_LAYER_CHANNEL; in aspeed_probe()
309 layers[1].size = 1; in aspeed_probe()
310 layers[1].is_virt_csrow = false; in aspeed_probe()
312 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in aspeed_probe()
H A Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
234 layers[0].size = 1; in octeon_lmc_edac_probe()
235 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
H A Dedac_mc.c70 edac_layer_name[mci->layers[i].type], in edac_dimm_info_location()
294 edac_layer_name[mci->layers[layer].type], in edac_mc_alloc_dimms()
307 if (mci->layers[0].is_virt_csrow) { in edac_mc_alloc_dimms()
324 if (pos[layer] < mci->layers[layer].size) in edac_mc_alloc_dimms()
335 struct edac_mc_layer *layers, in edac_mc_alloc() argument
352 tot_dimms *= layers[idx].size; in edac_mc_alloc()
354 if (layers[idx].is_virt_csrow) in edac_mc_alloc()
355 tot_csrows *= layers[idx].size; in edac_mc_alloc()
357 tot_channels *= layers[idx].size; in edac_mc_alloc()
359 if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) in edac_mc_alloc()
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H A Dfsl_ddr_edac.c496 struct edac_mc_layer layers[2]; in fsl_mc_err_probe() local
506 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in fsl_mc_err_probe()
507 layers[0].size = 4; in fsl_mc_err_probe()
508 layers[0].is_virt_csrow = true; in fsl_mc_err_probe()
509 layers[1].type = EDAC_MC_LAYER_CHANNEL; in fsl_mc_err_probe()
510 layers[1].size = 1; in fsl_mc_err_probe()
511 layers[1].is_virt_csrow = false; in fsl_mc_err_probe()
512 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in fsl_mc_err_probe()
H A Dal_mc_edac.c219 struct edac_mc_layer layers[1]; in al_mc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in al_mc_edac_probe()
234 layers[0].size = 1; in al_mc_edac_probe()
235 layers[0].is_virt_csrow = false; in al_mc_edac_probe()
236 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in al_mc_edac_probe()
H A Dbluefield_edac.c356 struct edac_mc_layer layers[1]; in bluefield_edac_mc_probe() local
384 layers[0].type = EDAC_MC_LAYER_SLOT; in bluefield_edac_mc_probe()
385 layers[0].size = dimm_count; in bluefield_edac_mc_probe()
386 layers[0].is_virt_csrow = true; in bluefield_edac_mc_probe()
388 mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv)); in bluefield_edac_mc_probe()
H A Dcpc925_edac.c910 struct edac_mc_layer layers[2]; in cpc925_probe() local
948 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cpc925_probe()
949 layers[0].size = CPC925_NR_CSROWS; in cpc925_probe()
950 layers[0].is_virt_csrow = true; in cpc925_probe()
951 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cpc925_probe()
952 layers[1].size = nr_channels; in cpc925_probe()
953 layers[1].is_virt_csrow = false; in cpc925_probe()
954 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in cpc925_probe()
H A Die31200_edac.c478 struct edac_mc_layer layers[2]; in ie31200_register_mci() local
485 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ie31200_register_mci()
486 layers[0].size = IE31200_RANKS_PER_CHANNEL; in ie31200_register_mci()
487 layers[0].is_virt_csrow = true; in ie31200_register_mci()
488 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ie31200_register_mci()
489 layers[1].size = nr_channels; in ie31200_register_mci()
490 layers[1].is_virt_csrow = false; in ie31200_register_mci()
491 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, in ie31200_register_mci()
H A Dti_edac.c237 struct edac_mc_layer layers[1]; in ti_edac_probe() local
251 layers[0].type = EDAC_MC_LAYER_ALL_MEM; in ti_edac_probe()
252 layers[0].size = 1; in ti_edac_probe()
259 mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac)); in ti_edac_probe()
H A Ddmc520_edac.c478 struct edac_mc_layer layers[1]; in dmc520_edac_probe() local
514 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in dmc520_edac_probe()
515 layers[0].size = dmc520_get_rank_count(reg_base); in dmc520_edac_probe()
516 layers[0].is_virt_csrow = true; in dmc520_edac_probe()
518 mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in dmc520_edac_probe()
H A Dversalnet_edac.c778 struct edac_mc_layer layers[2]; in init_one_mc() local
808 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in init_one_mc()
809 layers[0].size = rank; in init_one_mc()
810 layers[0].is_virt_csrow = true; in init_one_mc()
811 layers[1].type = EDAC_MC_LAYER_CHANNEL; in init_one_mc()
812 layers[1].size = num_chans; in init_one_mc()
813 layers[1].is_virt_csrow = false; in init_one_mc()
820 mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv)); in init_one_mc()
H A Darmada_xp_edac.c288 struct edac_mc_layer layers[1]; in axp_mc_probe() local
306 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in axp_mc_probe()
307 layers[0].size = SDRAM_NUM_CS; in axp_mc_probe()
308 layers[0].is_virt_csrow = true; in axp_mc_probe()
310 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata)); in axp_mc_probe()
H A Dnpcm_edac.c343 struct edac_mc_layer layers[1]; in edac_probe() local
371 layers[0].type = EDAC_MC_LAYER_ALL_MEM; in edac_probe()
372 layers[0].size = 1; in edac_probe()
374 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in edac_probe()
/linux/drivers/parisc/
H A Dpdc_stable.c358 for (i = 0; i < 6 && devpath->layers[i]; i++) in pdcspath_layer_read()
359 out += sprintf(out, "%u ", devpath->layers[i]); in pdcspath_layer_read()
381 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ in pdcspath_layer_write() local
393 memset(&layers, 0, sizeof(layers)); in pdcspath_layer_write()
398 layers[0] = simple_strtoul(in, NULL, 10); in pdcspath_layer_write()
399 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); in pdcspath_layer_write()
405 layers[i] = simple_strtoul(temp, NULL, 10); in pdcspath_layer_write()
406 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); in pdcspath_layer_write()
414 memcpy(&entry->devpath.layers, &layers, sizeof(layers)); in pdcspath_layer_write()
/linux/fs/overlayfs/
H A Dsuper.c1024 struct ovl_fs_context *ctx, struct ovl_layer *layers) in ovl_get_layers() argument
1110 layers[ofs->numlayer].trap = trap; in ovl_get_layers()
1111 layers[ofs->numlayer].mnt = mnt; in ovl_get_layers()
1112 layers[ofs->numlayer].idx = ofs->numlayer; in ovl_get_layers()
1113 layers[ofs->numlayer].fsid = fsid; in ovl_get_layers()
1114 layers[ofs->numlayer].fs = &ofs->fs[fsid]; in ovl_get_layers()
1173 struct ovl_layer *layers) in ovl_get_lowerstack() argument
1209 err = ovl_get_layers(sb, ofs, ctx, layers); in ovl_get_lowerstack()
1224 lowerstack[i].layer = &ofs->layers[i + 1]; in ovl_get_lowerstack()
1295 ofs->layers[i].mnt->mnt_root, in ovl_check_overlapping_layers()
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_hwrt.c49 hwrt->max_rts = args->layers; in hwrt_init_kernel_structure()
387 rta_ctl->max_rts = args->layers; in hwrt_data_init_fw_structure()
389 if (args->layers > 1) { in hwrt_data_init_fw_structure()
390 err = pvr_fw_object_create(pvr_dev, args->layers * SRTC_ENTRY_SIZE, in hwrt_data_init_fw_structure()
398 err = pvr_fw_object_create(pvr_dev, args->layers * RAA_ENTRY_SIZE, in hwrt_data_init_fw_structure()
418 if (args->layers > 1) in hwrt_data_init_fw_structure()
422 if (args->layers > 1) in hwrt_data_init_fw_structure()
/linux/Documentation/driver-api/fpga/
H A Dintro.rst9 * The FPGA subsystem separates upper layers (userspace interfaces and
10 enumeration) from lower layers that know how to program a specific
13 * Code should not be shared between upper and lower layers. This
/linux/Documentation/scsi/
H A Dscsi_eh.rst152 Note that this does not mean lower layers are quiescent. If a LLDD
153 completed a scmd with error status, the LLDD and lower layers are
155 has timed out, unless hostt->eh_timed_out() made lower layers forget
157 active as long as lower layers are concerned and completion could
206 lower layers and lower layers are ready to process or fail the scmd
364 that lower layers have forgotten about the scmd and we can
373 and STU doesn't make lower layers forget about those
375 if STU succeeds leaving lower layers in an inconsistent
428 On completion, the handler should have made lower layers forget about
468 - Know that timed out scmds are still active on lower layers. Make
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/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.c82 pos = to_cpos(pipe->layers[id - KOMEDA_COMPONENT_LAYER0]); in komeda_pipeline_get_component_pos()
302 if (left->layer_type == pipe->layers[i]->layer_type) in komeda_get_layer_split_right_layer()
303 return pipe->layers[i]; in komeda_get_layer_split_right_layer()
320 layer = pipe->layers[i]; in komeda_pipeline_assemble()

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