Searched refs:lane_status (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/hisilicon/hibmc/dp/ |
| H A D | dp_link.c | 139 u8 lane_status[DP_LINK_STATUS_SIZE]) in hibmc_dp_link_get_adjust_train()
145 train_set[lane] = drm_dp_get_adjust_request_voltage(lane_status, lane) | in hibmc_dp_link_get_adjust_train()
146 drm_dp_get_adjust_request_pre_emphasis(lane_status, lane); in hibmc_dp_link_get_adjust_train()
200 u8 lane_status[DP_LINK_STATUS_SIZE] = {0}; in hibmc_dp_link_training_cr() local
215 ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status); in hibmc_dp_link_training_cr()
221 if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_cr()
233 level_changed = hibmc_dp_link_get_adjust_train(dp, lane_status); in hibmc_dp_link_training_cr()
257 u8 lane_status[DP_LINK_STATUS_SIZE] = {0}; in hibmc_dp_link_training_channel_eq() local
268 ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status); in hibmc_dp_link_training_channel_eq()
274 if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { in hibmc_dp_link_training_channel_eq()
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| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | mdio_10g.h | 42 int i, lane_status; in ef4_mdio_phyxgxs_lane_sync() local
46 lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS, in ef4_mdio_phyxgxs_lane_sync()
49 sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN); in ef4_mdio_phyxgxs_lane_sync()
52 lane_status); in ef4_mdio_phyxgxs_lane_sync()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_8b_10b.c | 231 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_8b_10b_clock_recovery_sequence()
352 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 1317 uint8_t lane_status; in cdv_intel_clock_recovery_ok() local
1320 lane_status = cdv_intel_get_lane_status(link_status, lane); in cdv_intel_clock_recovery_ok()
1321 if ((lane_status & DP_LANE_CR_DONE) == 0) in cdv_intel_clock_recovery_ok()
1336 uint8_t lane_status; in cdv_intel_channel_eq_ok() local
1344 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane); in cdv_intel_channel_eq_ok()
1345 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) in cdv_intel_channel_eq_ok()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 1043 union lane_status *status, in get_lane_status()
1076 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in poll_for_allocation_change_trigger()
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