| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_capability.c | 67 enum dc_lane_count lane_count; member
102 .lane_count = LANE_COUNT_ONE,
493 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
495 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
503 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
505 switch (lane_count) { in reduce_lane_count()
552 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
554 switch (lane_count) { in increase_lane_count()
624 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
634 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
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| H A D | link_dp_training_8b_10b.c | 125 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
230 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
298 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
337 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
350 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
403 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
409 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
410 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
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| H A D | link_dp_training_fixed_vs_pe_retimer.h | 39 uint8_t lane_count);
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 84 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
86 return (lane_count == 1 || in is_lane_count_valid()
87 lane_count == 2 || in is_lane_count_valid()
88 lane_count == 4); in is_lane_count_valid()
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| H A D | dp_audio.h | 21 u32 lane_count; member
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| H A D | dp_audio.c | 208 switch (audio->msm_dp_audio.lane_count) { in msm_dp_audio_safe_to_exit_level()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 263 uint8_t lane_count; member
897 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
916 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
920 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
928 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
933 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
990 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1007 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp.c | 387 int lane_count; in intel_dp_max_lane_count() local
390 lane_count = forced_lane_count(intel_dp); in intel_dp_max_lane_count()
392 lane_count = intel_dp->link.max_lane_count; in intel_dp_max_lane_count()
394 switch (lane_count) { in intel_dp_max_lane_count()
398 return lane_count; in intel_dp_max_lane_count()
400 MISSING_CASE(lane_count); in intel_dp_max_lane_count()
413 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, in intel_dp_link_bw_overhead() argument
427 overhead = drm_dp_bw_overhead(lane_count, hdisplay, in intel_dp_link_bw_overhead()
443 int intel_dp_link_required(int link_clock, int lane_count, in intel_dp_link_required() argument
447 int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, in intel_dp_link_required()
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| H A D | intel_dsi.c | 40 return intel_dsi->pclk * bpp / intel_dsi->lane_count; in intel_dsi_bitrate()
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| H A D | g4x_dp.c | 103 pipe_config->lane_count); in intel_dp_prepare()
128 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
389 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; in intel_dp_get_config()
705 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); in intel_enable_dp()
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| H A D | intel_dp_tunnel.c | 60 int lane_count = intel_dp_max_common_lane_count(intel_dp); in get_current_link_bw() local
62 return intel_dp_max_link_data_rate(intel_dp, rate, lane_count); in get_current_link_bw()
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| H A D | icl_dsi.c | 355 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
436 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
831 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
928 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
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| H A D | intel_display_types.h | 1206 u8 lane_count; member
1798 u8 lane_count; member
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| H A D | intel_psr.c | 1372 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
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| H A D | intel_display.c | 5300 PIPE_CONF_CHECK_I(lane_count); in intel_pipe_config_compare()
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| /linux/include/drm/display/ |
| H A D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
63 int lane_count);
65 int lane_count);
1023 int drm_dp_bw_overhead(int lane_count, int hactive,
1030 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | audio_types.h | 42 enum dc_lane_count lane_count; member
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | link_encoder.h | 237 uint32_t lane_count; member
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 1042 uint32_t lane_count, in get_lane_status() argument
1059 for (lane = 0; lane < lane_count; lane++) { in get_lane_status()
1083 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); in poll_for_allocation_change_trigger()
1085 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
1086 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
1087 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
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| H A D | link_detection.c | 542 link->cur_link_settings.lane_count = in read_current_link_settings_on_detect()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 1804 union lane_count_set lane_count; in dp_get_link_current_set_bw() local
1816 lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; in dp_get_link_current_set_bw()
1819 dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); in dp_get_link_current_set_bw()
1851 …*cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_ef… in dp_get_link_current_set_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 813 enum dc_lane_count lane_count = in dcn401_enable_stream_calc() local
814 pipe_ctx->stream->link->cur_link_settings.lane_count; in dcn401_enable_stream_calc()
833 if (lane_count != 0) in dcn401_enable_stream_calc()
834 *early_control = active_total_with_borders % lane_count; in dcn401_enable_stream_calc()
837 *early_control = lane_count; in dcn401_enable_stream_calc()
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