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Searched refs:lane_count (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c67 enum dc_lane_count lane_count; member
102 .lane_count = LANE_COUNT_ONE,
493 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
495 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
503 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
505 switch (lane_count) { in reduce_lane_count()
552 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
554 switch (lane_count) { in increase_lane_count()
624 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
634 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
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H A Dlink_dp_training_8b_10b.c125 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
230 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
298 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
337 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
350 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
403 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
409 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
410 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
H A Dlink_dp_training_fixed_vs_pe_retimer.h39 uint8_t lane_count);
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c230 int lane, lane_count, retval; in analogix_dp_link_start() local
232 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
237 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
252 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
256 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
284 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
289 lane_count); in analogix_dp_link_start()
304 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
309 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h84 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
86 return (lane_count == 1 || in is_lane_count_valid()
87 lane_count == 2 || in is_lane_count_valid()
88 lane_count == 4); in is_lane_count_valid()
H A Ddp_audio.h21 u32 lane_count; member
H A Ddp_audio.c208 switch (audio->msm_dp_audio.lane_count) { in msm_dp_audio_safe_to_exit_level()
H A Ddp_ctrl.c2234 int lane_count) in msm_dp_ctrl_clock_recovery_any_ok() argument
2238 if (lane_count <= 1) in msm_dp_ctrl_clock_recovery_any_ok()
2246 reduced_cnt = lane_count >> 1; in msm_dp_ctrl_clock_recovery_any_ok()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c74 int lane_count; member
1257 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1264 .lanes = lane_count, in mtk_dp_phy_configure()
1428 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1450 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1483 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1521 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1818 u8 lane_count, link_rate, train_limit, max_link_rate; in mtk_dp_training() local
1823 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
1836 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count); in mtk_dp_training()
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/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.c305 enum dc_lane_count lane_count, in get_av_stream_map_lane_count() argument
312 av_stream_map_lane_count = lane_count; in get_av_stream_map_lane_count()
326 enum dc_lane_count lane_count, in get_audio_sdp_overhead() argument
335 audio_sdp_overhead = lane_count * 2 + 8; in get_audio_sdp_overhead()
454 available_hblank_bw *= dp_link_info->lane_count; in calculate_available_hblank_bw_in_symbols()
487 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); in check_audio_bandwidth_dp()
489 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); in check_audio_bandwidth_dp()
H A Ddce_clk_mgr.c531 cfg->link_settings.lane_count = in dce110_fill_display_configs()
532 stream->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.c63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
64 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c167 (unsigned char *)(&link_settings.lane_count), in dp_test_send_link_training()
182 link->verified_link_cap.lane_count = link_settings.lane_count; in dp_test_send_link_training()
437 (unsigned int)(link->cur_link_settings.lane_count); in dp_test_send_phy_test_pattern()
715 p_link_settings->link_settings.lane_count); in dp_set_test_pattern()
1008 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN; in dp_set_preferred_training_settings()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_link_encoder.c220 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
280 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn20_link_encoder_get_max_link_cap()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_link_encoder.c193 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn32_link_encoder_get_max_link_cap()
/linux/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h42 enum dc_lane_count lane_count; member
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c1177 uint32_t lane_count, in get_lane_status() argument
1194 for (lane = 0; lane < lane_count; lane++) { in get_lane_status()
1218 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); in poll_for_allocation_change_trigger()
1220 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
1221 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
1222 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || in poll_for_allocation_change_trigger()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio.c470 lanes = crtc_state->lane_count; in calc_hblank_early_prog()
508 lanes = crtc_state->lane_count; in calc_samples_room()
1011 crtc_state->lane_count == 4) { in intel_audio_min_cdclk()
H A Dintel_display_types.h1177 u8 lane_count; member
1758 u8 lane_count; member
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c1802 union lane_count_set lane_count; in dp_get_link_current_set_bw() local
1814 lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; in dp_get_link_current_set_bw()
1817 dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); in dp_get_link_current_set_bw()
1849 …*cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_ef… in dp_get_link_current_set_bw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c3022 enum dc_lane_count lane_count = in dcn20_enable_stream() local
3023 pipe_ctx->stream->link->cur_link_settings.lane_count; in dcn20_enable_stream()
3091 if (lane_count != 0) in dcn20_enable_stream()
3092 early_control = active_total_with_borders % lane_count; in dcn20_enable_stream()
3095 early_control = lane_count; in dcn20_enable_stream()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c914 enum dc_lane_count lane_count = in dcn401_enable_stream_calc() local
915 pipe_ctx->stream->link->cur_link_settings.lane_count; in dcn401_enable_stream_calc()
934 if (lane_count != 0) in dcn401_enable_stream_calc()
935 *early_control = active_total_with_borders % lane_count; in dcn401_enable_stream_calc()
938 *early_control = lane_count; in dcn401_enable_stream_calc()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h155 enum dc_lane_count lane_count; member

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