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Searched refs:lane_count (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c67 enum dc_lane_count lane_count; member
102 .lane_count = LANE_COUNT_ONE,
493 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
495 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
503 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
505 switch (lane_count) { in reduce_lane_count()
552 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
554 switch (lane_count) { in increase_lane_count()
624 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count in decide_fallback_link_setting_max_bw_policy()
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H A Dlink_dp_training_8b_10b.c125 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
230 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
298 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
337 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
350 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
403 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
409 if (dp_is_ch_eq_done(lane_count, dpcd_lane_statu in perform_8b_10b_channel_equalization_sequence()
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H A Dlink_dp_training_fixed_vs_pe_retimer.h39 uint8_t lane_count);
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h82 * @lane_count: lane count requested by the sink
86 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid()
88 return (lane_count == 1 || in is_lane_count_valid()
89 lane_count == 2 || in is_lane_count_valid()
90 lane_count == 4);
84 is_lane_count_valid(u32 lane_count) is_lane_count_valid() argument
H A Ddp_audio.h21 u32 lane_count; member
H A Ddp_audio.c208 switch (audio->msm_dp_audio.lane_count) { in msm_dp_audio_safe_to_exit_level()
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c263 uint8_t lane_count; member
897 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
916 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
920 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
928 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
933 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
990 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1007 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c398 int lane_count; in intel_dp_max_lane_count()
401 lane_count = forced_lane_count(intel_dp); in intel_dp_max_lane_count()
403 lane_count = intel_dp->link.max_lane_count; in intel_dp_max_lane_count()
405 switch (lane_count) { in intel_dp_min_lane_count()
409 return lane_count; in intel_dp_min_lane_count()
411 MISSING_CASE(lane_count); in intel_dp_min_lane_count()
424 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, in intel_dp_link_bw_overhead()
438 overhead = drm_dp_bw_overhead(lane_count, hdisplay,
454 int intel_dp_link_required(int link_clock, int lane_count,
458 int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdispla
387 int lane_count; intel_dp_max_lane_count() local
413 intel_dp_link_bw_overhead(int link_clock,int lane_count,int hdisplay,int dsc_slice_count,int bpp_x16,unsigned long flags) intel_dp_link_bw_overhead() argument
443 intel_dp_link_required(int link_clock,int lane_count,int mode_clock,int mode_hdisplay,int link_bpp_x16,unsigned long bw_overhead_flags) intel_dp_link_required() argument
758 intel_dp_link_config_get(struct intel_dp * intel_dp,int idx,int * link_rate,int * lane_count) intel_dp_link_config_get() argument
772 intel_dp_link_config_index(struct intel_dp * intel_dp,int link_rate,int lane_count) intel_dp_link_config_index() argument
813 intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count) intel_dp_link_params_valid() argument
1836 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); intel_dp_compute_link_config_wide() local
2048 is_bw_sufficient_for_dsc_config(struct intel_dp * intel_dp,int link_clock,int lane_count,int mode_clock,int mode_hdisplay,int dsc_slice_count,int link_bpp_x16,unsigned long bw_overhead_flags) is_bw_sufficient_for_dsc_config() argument
2071 int link_rate, lane_count; dsc_compute_link_config() local
2588 intel_dp_mode_valid_with_dsc(struct intel_connector * connector,int link_clock,int lane_count,int mode_clock,int mode_hdisplay,int num_joined_pipes,enum intel_output_format output_format,int pipe_bpp,unsigned long bw_overhead_flags) intel_dp_mode_valid_with_dsc() argument
3630 intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count) intel_dp_set_link_params() argument
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H A Dintel_dsi.c40 return intel_dsi->pclk * bpp / intel_dsi->lane_count; in intel_dsi_bitrate()
H A Dg4x_dp.c103 pipe_config->lane_count); in intel_dp_prepare()
128 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
389 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; in intel_dp_get_config()
705 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); in intel_enable_dp()
H A Dintel_dp_tunnel.c60 int lane_count = intel_dp_max_common_lane_count(intel_dp); in get_current_link_bw() local
62 return intel_dp_max_link_data_rate(intel_dp, rate, lane_count); in get_current_link_bw()
H A Dicl_dsi.c355 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
436 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
831 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
928 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
H A Dintel_display_types.h1207 u8 lane_count; member
1802 u8 lane_count;
1830 /* common rate,lane_count configs in bw order */
1801 u8 lane_count; global() member
/linux/include/drm/display/
H A Ddrm_dp_helper.h37 int lane_count);
39 int lane_count);
63 int lane_count);
65 int lane_count);
1024 int drm_dp_bw_overhead(int lane_count, int hactive,
1031 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c150 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
174 * echo <lane_count> <link_rate> > link_settings
213 link->cur_link_settings.lane_count, in dp_link_settings_read()
220 link->verified_link_cap.lane_count, in dp_link_settings_read()
227 link->reported_link_cap.lane_count, in dp_link_settings_read()
234 link->preferred_link_setting.lane_count, in dp_link_settings_read()
268 /* 0: lane_count; 1: link_rate */ in dp_link_settings_write()
332 /* save user force lane_count, link_rate to preferred settings in dp_link_settings_write()
337 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
402 /* 0: lane_count; in dp_mst_link_setting()
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H A Damdgpu_dm_mst_types.c1883 union lane_count_set lane_count; in dm_dp_mst_is_port_support_mode()
1895 lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; in dm_dp_mst_is_port_support_mode()
1898 dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); in dm_dp_mst_is_port_support_mode()
1930 *cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000; in dm_dp_mst_is_port_support_mode()
1804 union lane_count_set lane_count; dp_get_link_current_set_bw() local
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c653 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
667 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder()
1277 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1316 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1356 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output()
1395 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output()
1484 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_dp_set_lane_settings()
1489 for (lane = 0; lane < link_settings->lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/linux/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h42 enum dc_lane_count lane_count; member
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dlink_encoder.h292 * @lane_count: FRL lane count.
294 uint32_t lane_count;
314 int lane_count);
413 uint32_t lane_count;
237 uint32_t lane_count; global() member
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c1121 uint32_t lane_count, in update_mst_stream_alloc_table()
1138 for (lane = 0; lane < lane_count; lane++) { in update_mst_stream_alloc_table()
1162 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); in update_mst_stream_alloc_table()
1164 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in update_mst_stream_alloc_table()
1165 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || in update_mst_stream_alloc_table()
1166 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || in update_mst_stream_alloc_table()
1042 get_lane_status(struct dc_link * link,uint32_t lane_count,union lane_status * status,union lane_align_status_updated * status_updated) get_lane_status() argument
H A Dlink_detection.c544 link->cur_link_settings.lane_count = in read_current_link_settings_on_detect()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c680 .lanes_number = link_settings->lane_count, in dce110_external_encoder_control()
723 enum dc_lane_count lane_count = in dce110_enable_stream() local
724 pipe_ctx->stream->link->cur_link_settings.lane_count; in dce110_enable_stream()
743 if (lane_count != 0) in dce110_enable_stream()
744 early_control = active_total_with_borders % lane_count; in dce110_enable_stream()
747 early_control = lane_count; in dce110_enable_stream()
1375 dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count; in populate_audio_dp_link_info()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c969 enum dc_lane_count lane_count = in dcn401_set_cursor_position()
970 pipe_ctx->stream->link->cur_link_settings.lane_count; in dcn401_set_cursor_position()
989 if (lane_count != 0) in dcn401_set_cursor_position()
990 *early_control = active_total_with_borders % lane_count; in dcn401_set_cursor_position()
993 *early_control = lane_count; in dcn401_set_cursor_position()
813 enum dc_lane_count lane_count = dcn401_enable_stream_calc() local
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h155 enum dc_lane_count lane_count; member

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