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Searched refs:lane_base (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c910 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_config_lpcdrx() local
918 writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
920 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
929 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_lane_settings() local
941 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
942 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i)); in dsi_phy_hw_v4_0_lane_settings()
949 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i)); in dsi_phy_hw_v4_0_lane_settings()
950 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i)); in dsi_phy_hw_v4_0_lane_settings()
951 writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i)); in dsi_phy_hw_v4_0_lane_settings()
952 writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
H A Ddsi_phy.c654 phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", &phy->lane_size); in dsi_phy_driver_probe()
655 if (IS_ERR(phy->lane_base)) in dsi_phy_driver_probe()
656 return dev_err_probe(dev, PTR_ERR(phy->lane_base), in dsi_phy_driver_probe()
857 if (phy->lane_base) in msm_dsi_phy_snapshot()
859 phy->lane_size, phy->lane_base, in msm_dsi_phy_snapshot()
H A Ddsi_phy.h100 void __iomem *lane_base; member