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Searched refs:lane_base (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/phy/spacemit/
H A Dphy-k3-common.c262 void __iomem *lane_base = lg->base + lg->data->offsets[i]; in k3_pcie_phy_init() local
264 val = readl(lane_base + PCIE_RX_REG1); in k3_pcie_phy_init()
266 writel(val, lane_base + PCIE_RX_REG1); in k3_pcie_phy_init()
285 void __iomem *lane_base = lg->base + lg->data->offsets[i]; in k3_pcie_phy_init() local
288 val = readl(lane_base + PHY_PU_SEL); in k3_pcie_phy_init()
290 writel(val, lane_base + PHY_PU_SEL); in k3_pcie_phy_init()
293 val = readl(lane_base + PHY_RESET_CFG); in k3_pcie_phy_init()
295 writel(val, lane_base + PHY_RESET_CFG); in k3_pcie_phy_init()
298 val = readl(lane_base + PHY_MODE_CFG); in k3_pcie_phy_init()
300 writel(val, lane_base + PHY_MODE_CFG); in k3_pcie_phy_init()
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c914 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_config_lpcdrx() local
922 writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
924 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
933 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_lane_settings() local
945 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
946 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i)); in dsi_phy_hw_v4_0_lane_settings()
953 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i)); in dsi_phy_hw_v4_0_lane_settings()
954 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i)); in dsi_phy_hw_v4_0_lane_settings()
955 writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i)); in dsi_phy_hw_v4_0_lane_settings()
956 writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
H A Ddsi_phy.h102 void __iomem *lane_base; member