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Searched refs:lane (Results 1 – 25 of 155) sorted by relevance

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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
397 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_set() argument
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
407 lane->priv->lane1_phy_regs : in comphy_lane_reg_set()
408 lane->priv->lane0_phy_regs; in comphy_lane_reg_set()
415 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_poll() argument
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H A Dphy-armada38x-comphy.c47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
84 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
85 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
91 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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/linux/drivers/net/dsa/b53/
H A Db53_serdes.c42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
181 #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) argument
184 #define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) argument
290 #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) argument
291 #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) argument
292 #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
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H A Dbxt_dpio_phy_regs.h28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
/linux/drivers/phy/tegra/
H A Dxusb.c115 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
118 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
126 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
133 lane->function = err; in tegra_xusb_lane_parse_dt()
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
191 struct phy *lane; in tegra_xusb_pad_register() local
199 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
208 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
223 lane = pad->ops->probe(pad, np, i); in tegra_xusb_pad_register()
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H A Dxusb-tegra210.c447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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H A Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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H A Dxusb-tegra186.c324 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
326 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
331 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
334 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
336 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
480 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
482 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
484 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
528 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
530 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dserdes.c29 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
31 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
235 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
242 lane = MV88E6341_PORT5_LANE; in mv88e6341_serdes_get_lane()
246 return lane; in mv88e6341_serdes_get_lane()
252 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
259 lane = MV88E6390_PORT9_LANE0; in mv88e6390_serdes_get_lane()
265 lane = MV88E6390_PORT10_LANE0; in mv88e6390_serdes_get_lane()
269 return lane; in mv88e6390_serdes_get_lane()
277 int lane = -ENODEV; in mv88e6390x_serdes_get_lane() local
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/linux/drivers/phy/
H A Dphy-xgene.c658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
699 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
701 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
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/linux/sound/soc/tegra/
H A Dtegra186_asrc.c108 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
115 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
120 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
172 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
195 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
205 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
224 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
226 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
229 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
232 asrc->lane[i in tegra186_asrc_out_hw_params()
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/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c21 unsigned int lane; member
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
64 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
159 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
165 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
187 t_data.lane = params->lane; in sdw_compute_master_ports()
205 if (params[i].lane != l) in _sdw_compute_port_params()
239 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
264 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
276 if (params[i].lane != l) in sdw_compute_group_params()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c230 int lane, lane_count, retval; in analogix_dp_link_start() local
237 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
238 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
269 dp->link_train.training_lane[lane] = in analogix_dp_link_start()
284 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
285 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
296 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
298 int shift = (lane & 1) * 4; in analogix_dp_get_lane_status()
299 u8 link_value = link_status[lane >> 1]; in analogix_dp_get_lane_status()
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
146 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); in mtk_pcie_efuse_read_for_lane()
151 snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); in mtk_pcie_efuse_read_for_lane()
159 lane); in mtk_pcie_efuse_read_for_lane()
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
283 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
289 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
430 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
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/linux/drivers/phy/samsung/
H A Dphy-gs101-ufs.c23 #define PHY_PMA_TRSV_ADDR(reg, lane) (PHY_APB_ADDR((reg) + \ argument
24 ((lane) * PHY_GS101_LANE_OFFSET)))
148 static int gs101_phy_wait_for_calibration(struct phy *phy, u8 lane) in gs101_phy_wait_for_calibration() argument
157 off = PHY_PMA_TRSV_ADDR(TRSV_REG338, lane); in gs101_phy_wait_for_calibration()
173 static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane) in gs101_phy_wait_for_cdr_lock() argument
182 PHY_PMA_TRSV_ADDR(TRSV_REG339, lane)); in gs101_phy_wait_for_cdr_lock()
190 PHY_PMA_TRSV_ADDR(TRSV_REG222, lane)); in gs101_phy_wait_for_cdr_lock()
192 ufs_phy->reg_pma + PHY_PMA_TRSV_ADDR(TRSV_REG222, lane)); in gs101_phy_wait_for_cdr_lock()
H A Dphy-samsung-ufs.h122 int (*wait_for_cal)(struct phy *phy, u8 lane);
123 int (*wait_for_cdr)(struct phy *phy, u8 lane);
152 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
153 int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
155 const struct samsung_ufs_phy_cfg *cfg, u8 lane);
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-errata.c51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
/linux/drivers/nvdimm/
H A Dbtt.c208 static int btt_log_group_read(struct arena_info *arena, u32 lane, in btt_log_group_read() argument
212 arena->logoff + (lane * LOG_GRP_SIZE), log, in btt_log_group_read()
329 static int btt_log_read(struct arena_info *arena, u32 lane, in btt_log_read() argument
336 ret = btt_log_group_read(arena, lane, &log); in btt_log_read()
344 old_ent, lane, log.ent[arena->log_index[0]].seq, in btt_log_read()
363 static int __btt_log_write(struct arena_info *arena, u32 lane, in __btt_log_write() argument
372 ns_off = arena->logoff + (lane * LOG_GRP_SIZE) + in __btt_log_write()
384 static int btt_flog_write(struct arena_info *arena, u32 lane, u32 sub, in btt_flog_write() argument
389 ret = __btt_log_write(arena, lane, sub, ent, NVDIMM_IO_ATOMIC); in btt_flog_write()
394 arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; in btt_flog_write()
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/linux/drivers/ata/
H A Dsata_highbank.c259 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
263 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in highbank_cphy_disable_overrides()
265 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in highbank_cphy_disable_overrides()
270 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
276 tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_override_tx_attenuation()
278 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
281 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
284 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
289 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
291 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_override_rx_mode()
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/linux/drivers/ufs/host/
H A Dufs-amd-versal2.c404 u32 time_left, reg, lane; in ufs_versal2_phy_ratesel() local
407 for (lane = 0; lane < activelanes; lane++) { in ufs_versal2_phy_ratesel()
409 ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), &reg); in ufs_versal2_phy_ratesel()
419 ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); in ufs_versal2_phy_ratesel()
424 ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), &reg); in ufs_versal2_phy_ratesel()
450 u32 lane, reg, rate = 0; in ufs_versal2_pwr_change_notify() local
488 for (lane = 0; lane < dev_req_params->lane_tx; lane++) { in ufs_versal2_pwr_change_notify()
489 ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), &reg); in ufs_versal2_pwr_change_notify()
494 ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); in ufs_versal2_pwr_change_notify()
/linux/drivers/thunderbolt/
H A Dlc.c100 u32 ctrl, lane; in tb_lc_set_port_configured() local
116 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
118 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
121 ctrl |= lane; in tb_lc_set_port_configured()
125 ctrl &= ~lane; in tb_lc_set_port_configured()
162 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
178 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
180 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
183 ctrl |= lane; in tb_lc_set_xdomain_configured()
185 ctrl &= ~lane; in tb_lc_set_xdomain_configured()
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-isys-csi2-reg.h169 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane) (0xc + (lane) * 8) argument
170 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_DLANE(lane) (0x10 + (lane) * 8) argument
/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c211 u8 lane; member
292 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
301 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
310 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
394 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance); in xpsgtr_wait_pll_lock()
435 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
439 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
440 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
443 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
484 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
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