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Searched refs:l2sw_reg_base (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mac.c22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_mac_hw_stop()
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_mac_hw_stop()
26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
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H A Dspl2sw_int.c129 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_rx_poll()
131 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_rx_poll()
202 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_tx_poll()
204 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_tx_poll()
218 status = readl(comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_ethernet_interrupt()
223 writel(status, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_ethernet_interrupt()
228 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_interrupt()
230 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_interrupt()
248 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_interrupt()
250 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_interrupt()
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H A Dspl2sw_mdio.c27 reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mdio_access()
38 writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mdio_access()
39 writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0); in spl2sw_mdio_access()
43 comm->l2sw_reg_base + L2SW_PHY_CNTL_REG1); in spl2sw_mdio_access()
49 reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mdio_access()
52 writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mdio_access()
H A Dspl2sw_driver.c38 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
40 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
133 writel(MAC_TRIG_L_SOC0, comm->l2sw_reg_base + L2SW_CPU_TX_TRIG); in spl2sw_ethernet_start_xmit()
348 comm->l2sw_reg_base = devm_platform_ioremap_resource(pdev, 0); in spl2sw_probe()
349 if (IS_ERR(comm->l2sw_reg_base)) in spl2sw_probe()
350 return PTR_ERR(comm->l2sw_reg_base); in spl2sw_probe()
H A Dspl2sw_phy.c21 reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mii_link_change()
51 writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mii_link_change()
H A Dspl2sw_define.h223 void __iomem *l2sw_reg_base; member