| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v10_3.c | 280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3() local
296 r = amdgpu_ring_alloc(kiq_ring, 7); in hiq_mqd_load_v10_3()
302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
303 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
313 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
315 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v10_3()
316 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v10_3()
317 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v10_3()
318 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v10_3()
319 amdgpu_ring_commit(kiq_ring); in hiq_mqd_load_v10_3()
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| H A D | amdgpu_gfx.c | 558 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_gfx_disable_kcq() local
575 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) in amdgpu_gfx_disable_kcq()
579 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * in amdgpu_gfx_disable_kcq()
587 kiq->pmf->kiq_unmap_queues(kiq_ring, in amdgpu_gfx_disable_kcq()
592 amdgpu_ring_commit(kiq_ring); in amdgpu_gfx_disable_kcq()
598 r = amdgpu_ring_test_helper(kiq_ring); in amdgpu_gfx_disable_kcq()
608 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_gfx_disable_kgq() local
632 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * in amdgpu_gfx_disable_kgq()
640 kiq->pmf->kiq_unmap_queues(kiq_ring, in amdgpu_gfx_disable_kgq()
645 amdgpu_ring_commit(kiq_ring); in amdgpu_gfx_disable_kgq()
675 struct amdgpu_ring *kiq_ring = &kiq->ring; amdgpu_gfx_mes_enable_kcq() local
714 struct amdgpu_ring *kiq_ring = &kiq->ring; amdgpu_gfx_enable_kcq() local
778 struct amdgpu_ring *kiq_ring = &kiq->ring; amdgpu_gfx_enable_kgq() local
[all...] |
| H A D | amdgpu_amdkfd_gfx_v11.c | 265 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v11() local
281 r = amdgpu_ring_alloc(kiq_ring, 7); in hiq_mqd_load_v11()
287 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v11()
288 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
298 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
300 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v11()
301 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v11()
302 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v11()
303 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v11()
304 amdgpu_ring_commit(kiq_ring); in hiq_mqd_load_v11()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in kgd_hiq_mqd_load() local
310 r = amdgpu_ring_alloc(kiq_ring, 7); in kgd_hiq_mqd_load()
316 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
317 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
327 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
329 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_hiq_mqd_load()
330 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
331 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_hiq_mqd_load()
332 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()
333 amdgpu_ring_commit(kiq_ring); in kgd_hiq_mqd_load()
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| H A D | gfx_v12_1.c | 97 static void gfx_v12_1_kiq_set_resources(struct amdgpu_ring *kiq_ring, in gfx_v12_1_kiq_set_resources() argument
100 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_1_kiq_set_resources()
101 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_1_kiq_set_resources()
103 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_1_kiq_set_resources()
104 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_1_kiq_set_resources()
105 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_1_kiq_set_resources()
106 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_1_kiq_set_resources()
107 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_1_kiq_set_resources()
108 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_1_kiq_set_resources()
111 static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, in gfx_v12_1_kiq_map_queues() argument
149 gfx_v12_1_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq) gfx_v12_1_kiq_unmap_queues() argument
183 gfx_v12_1_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq) gfx_v12_1_kiq_query_status() argument
203 gfx_v12_1_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub) gfx_v12_1_kiq_invalidate_tlbs() argument
[all...] |
| H A D | amdgpu_amdkfd_gfx_v9.c | 305 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load() local
321 r = amdgpu_ring_alloc(kiq_ring, 7); in kgd_gfx_v9_hiq_mqd_load()
327 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
328 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
338 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
340 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
341 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
342 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
343 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
344 amdgpu_ring_commit(kiq_ring); in kgd_gfx_v9_hiq_mqd_load()
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| H A D | gfx_v9_0.c | 927 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, in gfx_v9_0_kiq_set_resources() argument
930 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_0_kiq_set_resources()
936 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
937 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
941 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
943 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
945 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx_v9_0_kiq_set_resources()
946 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx_v9_0_kiq_set_resources()
947 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
948 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
951 gfx_v9_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring) gfx_v9_0_kiq_map_queues() argument
981 gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq) gfx_v9_0_kiq_unmap_queues() argument
1009 gfx_v9_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq) gfx_v9_0_kiq_query_status() argument
1031 gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub) gfx_v9_0_kiq_invalidate_tlbs() argument
1044 gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring * kiq_ring,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t xcc_id,uint32_t vmid) gfx_v9_0_kiq_reset_hw_queue() argument
5725 struct amdgpu_ring *kiq_ring = &kiq->ring; gfx_v9_0_ring_preempt_ib() local
7201 struct amdgpu_ring *kiq_ring = &kiq->ring; gfx_v9_0_reset_kgq() local
7265 struct amdgpu_ring *kiq_ring = &kiq->ring; gfx_v9_0_reset_kcq() local
[all...] |
| H A D | gfx_v12_0.c | 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, in gfx_v12_0_kiq_set_resources() argument
295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_0_kiq_set_resources()
298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_0_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_0_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_0_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_0_kiq_set_resources()
306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, in gfx_v12_0_kiq_map_queues() argument
349 gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq) gfx_v12_0_kiq_unmap_queues() argument
383 gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq) gfx_v12_0_kiq_query_status() argument
403 gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub) gfx_v12_0_kiq_invalidate_tlbs() argument
4626 struct amdgpu_ring *kiq_ring = &kiq->ring; gfx_v12_0_ring_preempt_ib() local
[all...] |
| H A D | amdgpu_amdkfd.c | 849 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_amdkfd_unmap_hiq() local
857 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) in amdgpu_amdkfd_unmap_hiq()
876 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { in amdgpu_amdkfd_unmap_hiq()
882 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); in amdgpu_amdkfd_unmap_hiq()
885 amdgpu_ring_commit(kiq_ring); in amdgpu_amdkfd_unmap_hiq()
891 r = amdgpu_ring_test_helper(kiq_ring); in amdgpu_amdkfd_unmap_hiq()
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| H A D | gfx_v11_0.c | 360 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx11_kiq_set_resources()
362 struct amdgpu_device *adev = kiq_ring->adev; in gfx11_kiq_set_resources()
368 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
369 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
372 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
373 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
374 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx11_kiq_set_resources()
375 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
376 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_map_queues() argument
377 amdgpu_ring_write(kiq_ring, in gfx11_kiq_map_queues()
356 gfx11_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask) gfx11_kiq_set_resources() argument
419 gfx11_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq) gfx11_kiq_unmap_queues() argument
453 gfx11_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq) gfx11_kiq_query_status() argument
474 gfx11_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub) gfx11_kiq_invalidate_tlbs() argument
6235 struct amdgpu_ring *kiq_ring = &kiq->ring; gfx_v11_0_ring_preempt_ib() local
[all...] |
| H A D | mes_v12_0.c | 1444 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v12_0_kiq_enable_queue() local
1450 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v12_0_kiq_enable_queue()
1456 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v12_0_kiq_enable_queue()
1458 r = amdgpu_ring_test_ring(kiq_ring); in mes_v12_0_kiq_enable_queue()
1461 kiq_ring->sched.ready = false; in mes_v12_0_kiq_enable_queue()
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| H A D | mes_v11_0.c | 1281 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_enable_queue()
1287 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v11_0_kiq_enable_queue()
1293 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v11_0_kiq_enable_queue()
1295 return amdgpu_ring_test_helper(kiq_ring);
1279 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; mes_v11_0_kiq_enable_queue() local
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| H A D | mes_v12_1.c | 1420 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; in mes_v12_1_queue_init()
1426 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v12_1_ring_init()
1432 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); in mes_v12_1_ring_init()
1434 r = amdgpu_ring_test_ring(kiq_ring); in mes_v12_1_ring_init()
1437 kiq_ring->sched.ready = false; in mes_v12_1_ring_init()
1352 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; mes_v12_1_kiq_enable_queue() local
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