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Searched refs:kiq (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gmc.c774 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; in amdgpu_gmc_flush_gpu_tlb_pasid()
775 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; in amdgpu_gmc_flush_gpu_tlb_pasid() local
810 ndw = kiq->pmf->invalidate_tlbs_size + 8; in amdgpu_gmc_flush_gpu_tlb_pasid()
813 ndw += kiq->pmf->invalidate_tlbs_size; in amdgpu_gmc_flush_gpu_tlb_pasid()
816 ndw += kiq->pmf->invalidate_tlbs_size; in amdgpu_gmc_flush_gpu_tlb_pasid()
818 spin_lock(&adev->gfx.kiq[inst].ring_lock); in amdgpu_gmc_flush_gpu_tlb_pasid()
821 spin_unlock(&adev->gfx.kiq[inst].ring_lock); in amdgpu_gmc_flush_gpu_tlb_pasid()
825 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 2, all_hub); in amdgpu_gmc_flush_gpu_tlb_pasid()
828 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, 0, all_hub); in amdgpu_gmc_flush_gpu_tlb_pasid()
830 kiq->pmf->kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub); in amdgpu_gmc_flush_gpu_tlb_pasid()
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H A Damdgpu_amdkfd.c820 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; in amdgpu_amdkfd_unmap_hiq() local
821 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_amdkfd_unmap_hiq()
826 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) in amdgpu_amdkfd_unmap_hiq()
846 spin_lock(&kiq->ring_lock); in amdgpu_amdkfd_unmap_hiq()
848 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { in amdgpu_amdkfd_unmap_hiq()
849 spin_unlock(&kiq->ring_lock); in amdgpu_amdkfd_unmap_hiq()
854 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); in amdgpu_amdkfd_unmap_hiq()
865 spin_unlock(&kiq->ring_lock); in amdgpu_amdkfd_unmap_hiq()
H A Dmes_v11_0.c1278 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v11_0_kiq_enable_queue() local
1279 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_enable_queue()
1282 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v11_0_kiq_enable_queue()
1285 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v11_0_kiq_enable_queue()
1291 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v11_0_kiq_enable_queue()
1303 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_queue_init()
1358 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v11_0_kiq_ring_init()
1360 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_ring_init()
1386 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_mqd_sw_init()
1493 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, in mes_v11_0_sw_fini()
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H A Dmes_v12_0.c1443 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v12_0_kiq_enable_queue() local
1444 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v12_0_kiq_enable_queue()
1447 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v12_0_kiq_enable_queue()
1450 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v12_0_kiq_enable_queue()
1456 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v12_0_kiq_enable_queue()
1473 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_queue_init()
1548 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v12_0_kiq_ring_init()
1550 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_kiq_ring_init()
1576 ring = &adev->gfx.kiq[0].ring; in mes_v12_0_mqd_sw_init()
1677 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, in mes_v12_0_sw_fini()
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H A Damdgpu_amdkfd_gfx_v10_3.c280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3()
295 spin_lock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v10_3()
322 spin_unlock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c265 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v11()
280 spin_lock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v11()
307 spin_unlock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v11()
H A Dgfx_v12_0.c357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
1644 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v12_0_sw_fini()
2805 adev->gfx.kiq[0].ring.sched.ready = enable; in gfx_v12_0_cp_compute_enable()
2964 (adev->doorbell_index.kiq * 2) << 2); in gfx_v12_0_cp_set_doorbell_range()
3329 (adev->doorbell_index.kiq * 2) << 2); in gfx_v12_0_kiq_init_register()
3430 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); in gfx_v12_0_kiq_resume()
3431 adev->gfx.kiq[0].ring.sched.ready = true; in gfx_v12_0_kiq_resume()
4585 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v12_0_ring_preempt_ib() local
4586 struct amdgpu_ring *kiq_ring = &kiq->ring; in gfx_v12_0_ring_preempt_ib()
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H A Dvega10_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; in vega10_doorbell_index_init()
H A Dvega20_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
H A Damdgpu_amdkfd_gfx_v10.c294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in kgd_hiq_mqd_load()
309 spin_lock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
336 spin_unlock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
H A Damdgpu_amdkfd_gfx_v9.c305 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load()
320 spin_lock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
347 spin_unlock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
H A Dsoc21.c520 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc21_init_doorbell_index()
H A Dgmc_v9_0.c835 if (adev->gfx.kiq[inst].ring.sched.ready && in gmc_v9_0_flush_gpu_tlb()